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Chapter 4 Award BIOS Setup
PCI DELAY TRANSACTION :
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles.
specification version 2.1.
PCI#2 ACCESS #1 RETRY :
When disabled, PCI#2 will not be disconnected until access finishes (default).
When enabled, PCI#2 will be disconnected if max retries are attempted
without success.
Page: 4-14
Select Enabled to support compliance with PCI
PPC-7365F USER
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S MANUAL
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