Yamaha RX-V461 Service Manual page 42

RX-V461/HTR-6040/RX-V461DAB
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Pin No. Function Name
41 ROUT3
42 NC
43 LOUT2
44 NC
45 ROUT2
46 NC
47 LOUT1
48 NC
49 ROUT1
50 NC
51 LIN
52 RIN
53 VCOM
54 VREFH
55 AVDD
56 AVSS
57 RX0
58 NC
TE
L 13942296513
59 RX1
60 TEST1
61 RX2
62 NC
63 RX3
64 PVSS
65 R
66 PVDD
67 RX4
68 TEST2
69 RX5
70 CAD0
71 RX6
72 CAD1
73 RX7
74 I2C
75 DAUX2
76 VIN
77 MCLK
78 TX0
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79 TX1
80 INT0
.
Note: All input pins except internal biased pins and internal pull-down pin should not be left floating.
42
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I/O
O DAC3 R ch analog output pin
No connect pin
–
No internal bonding / This pin should be opened
O DAC2 L ch analog output pin
No connect pin
–
No internal bonding / This pin should be opened
O DAC2 R ch analog output pin
No connect pin
–
No internal bonding / This pin should be opened
O DAC1 L ch analog output pin
No connect pin
–
No internal bonding / This pin should be opened
O DAC1 R ch analog output pin
No connect pin
–
No internal bonding / This pin should be opened
I L ch analog input pin
I R ch analog input pin
Common voltage output pin
–
2.2 F capacitor should be connected to AVSS externally
– Positive voltage reference input pin, AVDD
– Analog power supply pin, 4.5 V to 4.5 V
– Analog ground pin, 0 V
I Receiver channel 0 pin (Internal biased pin / Internally biased at PVDD/2)
No connect pin
–
No internal bonding / This pin should be connected to PVSS
I Receiver channel 1 pin (Internal biased pin / Internally biased at PVDD/2)
Test 1 pin
I
This pin should be connected to PVSS
I Receiver channel 2 pin (Internal biased pin / Internally biased at PVDD/2)
No connect pin
–
No internal bonding / This pin should be connected to PVSS
I Receiver channel 3 pin (Internal biased pin / Internally biased at PVDD/2)
– PLL ground pin
External resistor pin
–
12 k-ohms +/-1 % resistor should be connected to PVSS externally
– PLL power supply pin, 4.5 V to 4.5 V
I Receiver channel 4 pin (Internal biased pin / Internally biased at PVDD/2)
Test 2 pin
I
This pin should be connected to PVSS
I Receiver channel 5 pin (Internal biased pin / Internally biased at PVDD/2)
I Chip address 0 pin (ADC/DAC part)
I Receiver channel 6 pin (Internal biased pin / Internally biased at PVDD/2)
I Chip address 1 pin (ADC/DAC part)
I Receiver channel 7 pin (Internal biased pin / Internally biased at PVDD/2)
Control mode select pin
I
"L": 4-wire serial, "H": I2C bus
I Auxiliary audio data input pin (DIR/DIT part)
I V-bit input pin for transmitter output
I Master clock input pin
O Transmit channel (through data) output 0 pin
Transmit channel output 1 pin
O When TX bit = "0", transmit channel (through data) output 1 pin.
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When TX bit = "1", transmit channel (DAUX2 data) output pin (default)
O Interrupt 0 pin
i
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2 9
8
Detail of Function
Q Q
3 6 7 1 3 1 5
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.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9