Pll Circuit - Vertex Standard VX-1210 Service Manual

Circuit Description
op-amp Q1053 (M5218AFP), the output which is buffered by
Q1055 (2SC2812), then fed back to the 2nd gate of the 47.055
MHz IF amplifier Q1048, so that transmitter IF gain is regulated
by relative power output, thus preventing overdrive or transmis-
sion into an excessive impedance mismatch at the antenna.

PLL Circuit

The PLL local signal for the receiver 1st local and the trans-
mitter final local is generated by one of three VCOs: Q2017,
Q2018, & Q2019 (all 2SK210GR) in conjunction with varactor
diodes D2008, D2009, & D2010 (all HVU359) on the CNTL
Unit. The oscillating frequency is determined primarily by the
level of DC voltage applied to the varactor diodes. The VCO
output is buffered by Q2011 (2SK302Y), amplified by Q2025
(2SC535B) and bandpass filtered by capacitor C2088, C2091,
C2093, C2095, C2096, & C2099 and coils L2012, L2013, L2015,
& L2016. The filtered PLL local signal is applied to the J1002
on the Main Unit, then fed through the buffer amplifiers Q1003
(2SC2714Y), Q1004 (2SC3356), and Q1005 (2SC2954) to
the TX final mixer/RX 1st mixer D1009.
A portion of the output of buffer amplifier Q2011 is further
amplified by Q2006 (2SC2714Y) and delivered to the PLL sub-
system IC Q2001 (LM7001JUM), which contains a reference
divider, serial-to-parallel data latch, programmable divider, phase
comparator and a swallow counter. The sample VCO signal is
divided by the programmable divider section of the Q2001.
Meanwhile, the 36.355 MHz crystal reference oscillator X2002
and Q2037 (2SC2714Y) amplified by Q2036 & Q2033 (both
2SC2714Y ) and is divided by the DDS IC Q2024
(AD9850BRS) in accordance with the PLL dividing data from
the main CPU Q2030 (HD64F2134FA20), then applied to the
low-pass filter which consist of capacitors C2034, C2036, C2037,
C2038, C2041, C2046, C2047, C2051, & C2053 and coils
L2002, L2003, L2004, & L2006. The divided and filtered refer-
ence signal is applied to the reference divider section of the PLL
subsystem IC Q2001, where divides it by 72 to produce the loop
reference.
The divided signal from the programmable divider (derived
from the VCO) and that derived from the reference oscillator are
applied to the phase detector section of the PLL subsystem IC
Q2001, which produces a pulsed output with pulse duration de-
pending on the phase difference between the input signals. This
pulse train is low-pass filtered by Q2003 (2SK208Y) & Q2004
(2SC2812), then fed back to the VCO varactor diodes D2008,
D2009, & D2010.
Changes in the DC voltage applied to the varactor diodes
D2008, D2009, and D2010 affect the reactance in the tank cir-
cuit VCO Q2017, Q2018, and Q2019, changing the oscillating
frequency according to the phase difference between the signals
derived from the VCO and the crystal reference oscillator. The
VCO is thus phase-locked to the reference frequency standard.
A portion of the output of reference signal from Q2037 is
buffered by Q2038 (2SC2714Y), then applied to the low-pass
filter which consist of capacitors C2155 ~ C2159 and coils L2024
20
& L2025. The filtered reference signal delivered to J1003 on the
Main Unit, then applied to the 2nd gate of the TX 1st mixer
Q1046 and 2nd gate of the RX 2nd mixer Q1006.
A portion of the output of reference signal from Q2033 is
applied to further DDS IC Q2032 (FQ7928) where the refer-
ence signal is devided to 10.7 MHz carrier signal accordance
with the PLL dividing data from the main CPU Q2030, then ap-
plied to the buffer amplifier Q2035 (2SC2812). The amplifed
carrier signal is fed through the low-pass filter consist of capaci-
tors C2117, C2119, & C2122 ~ C2126 and coils L2020 ~ L2022
to J1005 on the Main Unit, then fed through the carrier amplifier
Q1022 (2SC2812) to the detector diode D1024 & D1025 and
balanced modulator D1036.
Control Circuit
Major frequency control functions such as memory select-
ing, display, and PLL divider control are performed by main CPU
Q2030 (HD64F2132RF) on the CNTL Unit, at the command
of the user via the tuning knob and function switches on the front
panel.
The programmable divider data for the PLL from main CPU
Q2030 is applied directly to DDS IC Q2024 (AD9850BRS) &
Q 2 0 3 2 ( F Q 7 9 2 8 ) a n d P L L s u b s y s t e m I C Q 2 0 0 1
(LM7001JUM).
The MODE selection data from the main CPU Q2030 is level
shifted by Q2007 ~ Q2010 (all FMC3) to control the various
circuit required for the selected mode.
The BAND selection binary data from the main CPU Q2030
is BCD-to Decimal decoded by Q2021 (TC4028BF). The re-
sulting decimal outputs are level shifted by Q2015 (TD62083F)
to select the active band-pass filter on the Main Unit required for
the operating frequency. Also, the decimal outputs from Q2021
are delivered to PA Unit, then level shifted by Q3001 ~ Q3006
and Q3009 (all FMC5A) to select the active low-pass filter re-
quired for the operating frequency.
TX/RX Control
When press the PTT switch, pin 22 of main CPU Q2030
(HD64F2134FA20) goes low. This signal disable the receiver
12 V bus at Q2022 (2SA1179). At the same time, activate the
transmit 12 V bus at Q2016 (2SA1365).
Power Supply & Regulation
The +5 V bus for the main CPU is derived from the 13.5 V
bus via regulator Q2050 (NJM78L05UA) on the CNTL Unit.
The +5 V bus is derived the from the 13.5 V bus by switching
regulator Q2043 (IR3M03A) and rectified D2016 (11EQS04)
and L2028. A portion of the +5 V is switched by Q2044
(2SC4047) & Q2047 (2SA1365) on the CNTL Unit, under con-
trol of the main CPU Q2030 via pin 58.
The +8 V bus is derived from the 13.5 V bus via regulator
Q2048 (KIA7808API) on the CNTL Unit.