Rx2 Circuit; Receive Signal Flow; Agc Circuit Operation; Carrier Oscillation Signal Circuit - Yaesu Mark-V FT-1000MP Field Technical Supplement

VCO1 uses the VCO0 control signal to drive switching tran-
sistors Q4039 (2SA1563) and Q4040 (2SC4047), applying a for-
ward bias to D4013 (1SV271), and switching C4173 into the os-
cillator circuit, producing a frequency shift.
The 70.555 ~ 100.455 MHz VCO signal is fed to mixer Q4001
(µPC1037) via buffer amplifier FET Q4007 (2SK210GR) and
buffer amplifier Q4006 (2SC2714Y).
The 3rd local signal (8.67 MHz) is buffer-amplified by Q4022
and passed through the LPF composed of capacitors C4112, C4113,
and C4118-C4120, coils L4026/ L4027; the reference oscillator
signal (10.48576 MHz) from the TCXO Unit that has been ampli-
fied by transistor Q4025 (2SC2812) is divided into 2.62144 MHz
by the 1/4-frequency divider Q4020 (TC74HC74AF), and passes
through a low-pass filter composed of capacitors C4105, C4106,
and C4108-C4110 and coils L402/L4025; these two signals are
applied to mixer Q4019 (SN16913) to obtain a 6.04856 MHz
signal.
This 6.04856 MHz signal is stripped of unwanted signal com-
ponents by ceramic filter CF4002 (SFT6.0MA) and fed to mixer
Q4010 (SN16913), together with the 291.16 ~ 373.08 kHz out-
put frequency of the DDS-PLL Unit, to obtain a 5.67548 ~ 5.75740
MHz signal. This signal passes through CF4001 (SFT-5.74MA)
to mixer Q4002 (µPC1037H), together with the 62.24 MHz 2nd
L.O. output that has been buffer-amplified by Q4011 (2SC2714Y),
to obtain a 67.91548 ~ 67.99740 MHz signal.
This signal passes through a BPF composed of T4003-T4005
and C4011/4012, is buffer-amplified by Q4008 (2SC2714Y), and
is fed to mixer Q4001 (µPC1037H) via transformer T4002.
The mixer output from Q4001 (2.62144 ~ 32.52224 MHz)
passes through a 9th-order Chebychev LPF composed of L4007-
L4011, C4048-C4052, and C4061-C4066, and is amplified by FETs
Q4015 (2SK210GR) and Q4018 (2SC2714Y), and then is de-
livered to PLL IC Q4024 (MB87088APF).
At the same time, the 10.48576 MHz reference oscillator sig-
nal from the TCXO Unit is fed to PLL IC Q4024 after it is ampli-
fied by Q4030 (2SC2812), the signal and passes through buffer
amplifier Q4028 (2SC2812) and a LPF composed of C4148,
C4149, and L4033.
The phase of the reference frequency and that of the signal
input to PLL IC is compared, and a signal whose pulse corresponds
to the phase difference is produced. The VCO frequency is con-
trolled by a loop filter which consists of an active filter composed
of Q4033 (2SK208Y), Q4034 (2SC2812), Q4038 (2SC2812),
R4089, R4091, and C4153 and a secondary lag filter composed of
C4059, C4095, C4128, C4160, C4158, and R4088.

Carrier Oscillation Signal Circuit

The 453.5 ~ 466.74 kHz (cf = 455.0 kHz) carrier output from
the DDS-CAR Unit passes through buffer amplifier Q3020
(2SC2812) and a LPF composed of C3063, C3064, and L3002.
The signal path is switched by D3003 and D3005 (both 1SS226)
during Tx/Rx so that the signal is properly delivered to balanced
modulator IC Q3046 and SSB detector Q3007.
Circuit Description

RX2 Circuit

Receive Signal Flow

A portion of the receive signal from the RF Unit may be deliv-
ered to J8002 of the RX2 Unit via J1010. It then passes through
T8008 and is fed to 1st mixer FETs Q8022 and Q8027 (both
SST310). The 47.31 ~ 77.21 MHz 1st L.O. signal output from the
RX2 PLL circuit is passed to the 1st mixer. The resulting 47.21
MHz 1st IF signal then passes through monolithic filter XF8001
(47G10AU, BW: ±20 kHz), is amplified by Q8024 (3SK131),
and is then fed on to the 2nd mixer circuit.
The 46.755 MHz 2nd L.O. and the 1st IF signal are mixed in
Q8023 and Q8026 (both 2SK302GR) to generate a 455 kHz 2nd
IF signal. This signal is then fed to noise-blanker noise amplifier
Q8008 (3SK131), noise gates D8010 and D8028 (both 1SS270),
and the FM signal buffer amplifier Q8001 (MC3372ML), respec-
tively.
The 2nd IF signal, now removed of noise by the noise gates, is
passed through either CF8002, CF8003, or U8001 to become the
desired signal component. It is then amplified by FETs Q8048 and
Q8049 (both 3SK131) and is fed to the SSB demodulator circuit
through a buffer amplifier.
The 2nd IF signal that has been delivered to the SSB demodu-
lator circuit is fed to IC Q8057 (µPC1037H), together with a car-
rier signal from the RX2 CAR-DDS Unit, and demodulated into
an audio signal.
The demodulated audio signal is removed of wide-band fre-
quency components as it passes through buffer amplifier transistor
Q8017 (2SC2812) and active LPF Q8013 (M5218AFP). It is
then passed to analog switch Q8006 (µPD4052BG).
The signal that has passed through the buffer amplifier is fed
on to the AM detector circuit and AGC circuit. An AM signal de-
tected by D8014 (2SC2812) is fed to analog switch Q8006.
The audio signal that has passed through analog switch Q8006
then passes through mute switch FET Q8002 (2SK160), and is
amplified by Q8015 (2SC2812), before input to the electronic
volume control on the AF Unit via connector J8001.

AGC Circuit Operation

The receive signal that has passed through buffer amplifier
Q8029 (2SC2812) is rectified by AGC detector D8017 and D8008
(both 1SS188) and fed to control gate 2 of FETs Q8024, Q8048,
and Q8049 (all 3SK131) by transistor Q8021 (2SC2812). This
signal is also amplified by op-amps Q8005 and Q8011 (both
M5223AFP) for S-meter and squelch control.
RX2 PLL Frequency Synthesizer
The 2nd L.O. circuit is a Hartley-type overtone oscillator cir-
cuit (frequency: 46.755 MHz) composed of FET Q8046
(2SK210GR), crystal X8001, and transformer T8018 (all on the

RX-2 Unit).

The oscillation signal from this circuit is fed to the 2nd mixer
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