Control Circuitry; Analog-Digital Converter Circuit (Receiving System); Digital-Analog Converter Circuit (Receiving System); Digital Signal Processor Circuit (Receiving System) - Yaesu Mark-V FT-1000MP Field Technical Supplement

frequency output of 455 kHz to ceramic filter CF2002 via connector
J2009 on the IF Unit. Thus, this circuit performs the same operations
as the analog circuit, but with greatly reduced noise.
When only the equalizing function is used in the A3 mode, the
circuit operations after balanced modulator IC Q3046 are the same
as those of the analog circuit.

Analog-Digital Converter Circuit (Receiving System)

The audio signal passing through balanced modulator IC Q3007
in the AF Unit, or the SSB signal of 10.24 kHz (suppressed car-
rier) is fed to the DSP-A Unit via connectors J3037/J7001. It then
passes through an inverting/non-inverting buffer amplifier circuit
composed of op-amplifier IC Q7006-2, then it flows to Q7006-4
(NJM3403AM), and finally is fed to A/D converter IC Q7001,
where it is converted into a 16-bit digital signal. As 16-bit serial
data, this signal is fed to DSP IC Q7101 in the DSP-D Unit via
connector J7003.

Digital-Analog Converter Circuit (Receiving System)

The serial digital data that is delivered to the D/A converter IC
Q7001 is converted into analog data and passed through a differ-
ential amplification type tertiary LPF (cut-off frequency = 18 kHz)
composed of op-amp ICs Q7008-1/Q7008-2 (µPC457G2),
R7037-R7043, and C7043-C7046 to suppress out-of-band quanti-
zation noise, etc. It is then fedto the AF Unit as an audio signal via
connector J7001.

Digital Signal Processor Circuit (Receiving System)

During receive, this circuit performs audio processing and SSB/
CW/AM demodulation. The A/D-converted signal data is subjected
to digital demodulation and audio processing. When appropriate,
it is possible to disable the digital demodulation and audio pro-
cessing.
When the DSP demodulation function is used, balanced mixer
IC Q3007 of the AF Unit operates as a double balanced mixer
(frequency mixer). In this case, the 3rd IF signal (455 kHz) from
the IF Unit is mixed with a carrier (local) signal of the frequency
(f = 466.74 kHz, f = 463.74 kHz) generated by the DDS-
LSB USB
CAR Unit to produce a differential frequency of 10.24 kHz. The
audio data processed by DSP IC is sent as serial data to the D/A
converter in the DSP-A Unit.

Control Circuitry

Microprocessor Circuit
The microprocessor circuit, which is composed of CPU IC
Q5008 (M37702E8BPF) and EEPROM IC Q5024 (M24C16-
VMNS), performs various types of processing, such as control
signals, serial I/O, A/D conversion, dial counter circuit control,
key input, and display functions.
The EEPROM memorizes various parameters and settings
(transmission frequency range, transmission output control) and
carrier points according to the transceiver version and the contents
of memory channels.
Circuit Description
Reset Circuit
The reset circuit consists mainly of CNTL Unit ICs Q5005
( M 5 1 9 4 5 B P F ) , Q 5 0 2 2 ( 2 S C 4 0 4 7 ) , a n d Q 5 0 3 9 - 5
(TC74HC04AF), capacitors, and resistors. This circuit controls
the power-down input port, CPU reset input, keyer CPU, and re-
lated circuits.
Dial Counter Circuit
The dial counter circuit consists of two VFO dials, the MEM
dial, the CLAR dial, and ICs Q5026 and Q5027 (both FQ7927).
This circuit detects a two-phase pulse having a phase difference of
90 degrees and delivers it to CPU IC Q5008 as 8-bit parallel data.
Control Circuit
The control circuitry consists of CNTL Unit ICs Q5023, Q5025,
Q5028-Q5039, etc. This circuitry controls the operation of vari-
ous switches, filters, transmit/receive modes, VCOs, bandswitching,
and the input of signals.
Serial Data Communication Circuit
Data transfer to the PLL IC, DDS-PLL, SUB, CAR, RX2-PLL,
RX2-CAR Unit, indicators, keyer, DSP, etc. is performed by a 3-
wire system clock synchronous communication, whereas internal
ANT tuner and CAT serial signals are transferred by 2-wire asyn-
chronous communications.
Various types of data, such as operating frequency, mode, and
display data, are processed by CPU IC Q5008 and transferred as
serial signals to the appropriate devices by ICs Q5013
( T C 7 4 H C 0 4 A F ) , Q 5 0 1 8 ( T C 7 4 H C 0 4 A F ) , Q 5 0 2 0
(µPD74HC238GS), Q5021 (µPD74HC238GS), and Q5037
(TC74HC32AF).
The CAT (external computer control) signals are converted to
RS232 interface standard levels by IC Q5006 (ADM232LJR) and
exit from pin 9 of DB-9 connector J5007.
Key Matrix Circuit
The key matrix circuit consists of DISPLAY Unit ICs Q5506
and Q5507 (both MC14028BPF), D5503-D5517 (all DAN202K),
and the panel key switches arranged on the matrix. When a key is
pressed, this circuit reads the input data for processing by the CPU.
Analog-Digital Converter Circuitry
Forward and reflected-wave voltage, ALC, power supply, S-
meter, COMP meter, IF SHIFT/WIDTH VR, DSP switch, PITCH
VR, Shuttle Jog, REMOTE terminal, etc. are selected by CNTL
Unit ICs Q5009/Q5010 (both MC14053BP) and Q5038
(MC14053BFR), and are fed to the A/D port of CPU IC Q5008
for conversion into digital values to be processed.
The individual voltages, converted into digital values, are dis-
played as PO, SWR, ALC, IC, VCC, and S-meter indications on
the LCD panel.
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