Power Control Circuit; Pll Circuit; Pll Block Diagram - Yaesu FT-480R Instruction Manual

POWER CONTROL CIRCUIT
When the HI/LOW switch is set to the LOW posi-
tion, the base of Qioas is grounded through VRjo:2,
and the collector current of Qjoa, is decreased.
Because the output power of Qjo9; is controlled
by Qroo3, the drive level to Qyo92 is decreased, thus
reducing the RF output power to approximately
| watt.
TONE BURST CIRCUIT
When the PTT switch is pressed, the one-shot
multivibrator consisting of Qiogo (A2, 3) (MC-
14011B) is activated to generate a pulse of 0.5—1
second duration. The pulse switches Qio5, (2SA-
733P) to supply DC voltage to Qios, (TC5082P),
where a 1750 or 1800 Hz tone signal is generated.
Pressing the T.CALL switch also switches Qj9s3 and
generates a tone signal. The tone is fed to the FM
MIC amplifier and superimposed on the transmit
signal.
ALC (Automatic Level Control) CIRCUIT
A portion of the output power from Qs. ts
applied through Cyo29 to rectifiers Dy99, and Doo.
producing a DC voltage. The DC voltage is ampli-
fied by DC amplifier Qioig (2SC1815Y) and fed to
gate 2 of Qiois to control its gain, thus preventing
overdrive. The ALC level is adjusted by VR,o93 for
proper drive to Qzoo2 -
AFP (Automatic Final Protection) CIRCUIT
If the transmitter is activated without an antenna
being connected, or if a high VSWR is present at
the antenna jack, the reflected power is detected
through T299,; and Dsoo3. The detected AFP voltage
is applied through VR2ioo2 to Qiog3 (2SC1815SY) in
the Main Unit. As the reflected power increases,
the AFP voltages also increases and consequently
Qioses conducts. The signal is fed to Qhuos
(2SC1815Y), this decreases the voltage at gate 2
of Qiows (3SK73Y), resulting in lower output
power. When the transceiver is correctly matched
to an antenna, full power output will be obtained.
PLL CIRCUIT
The PLL circuit is comprised of three PLL oscil-
lators each consisting of a reference crystal oscil-
lator, a programmable divider, a prescaler, and a
phase comparator. The PLL produces local signals
for the receiver and transmitter stages, using a
synthesis scheme which produces 10 Hz steps.
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FT-480R
PLL BLOCK DIAGRAM
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—---- CONT,
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