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Pin No.
Terminal name
36
OD1
37
HVDD2
38
D0
39
GND
40
DX
41
CINT
42
GND
43
SDA
44
CVDD
45
D1
46
D2
47
RSTB
48*
CBREQ
49
D3
50
D4
51
TEST2
52
STANDBY
53
TEST1
54
GND
55
PCLK
56
HSYNC
57
D7
58
D5
59*
–
60
TEST3
61
ACL
62
SDC
63
HVDD1
64
GND
65
VSYNC
66
HVDD1
67
D6
68*
–
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
EXCKI
Clock control circuit
Host side
Host I/F
Image data
CONFIDENTIAL
Input/Output
Input/Output
CPU I/F data bus, bit 1
–
External digital power supply 2 (+1.8/3.0 V)
Input
Image I/F input data, bit 0
–
Earth
Input
Test terminal (use Low input)
Output
CPU/ I/F interrupt output
–
Earth
Input/Output
Artificial I C I/F data line
2
–
Internal core power supply (+1.8 V)
Input
Image I/F input data, bit 1
Input
Image I/F input data, bit 2
Input
Reset input
Output
CPU I/F DMA request output (Not used)
Input
Image I/F input data, bit 3
Input
Image I/F input data, bit 4
Input
Test terminal 2
Output
Stand-by signal output to camera module
Input
Test terminal 1
–
Earth
Input
Input pixel clock from camera module
Input
Horizontal synchronous signal
Input
Image I/F input data, bit 7
Input
Image I/F input data, bit 5
–
Continuity test terminal (Not used)
Input
Test terminal 3
Output
Reset signal output to camera module
Input/Output
Artificial I C I/F clock line
2
–
External digital power supply 1 (+3.0 V)
–
Earth
Input
Vertical synchronous signal
–
External digital power supply 1 (+3.0 V)
Input
Image I/F input data, bit 6
–
Continuity test terminal (Not used)
Line buffer
for saving
Shared
memory
640x16x8
Line buffer
for display
Image processing block
Control data
Description of terminal
Artificial I
generation circuit
YUV serial/parallel
conversion
Format conversion
(e.g. image trimming)
(UYVY-YUV)
(UYVY-RGB)
Reduction
192x16x1
320x16x2
DSP control circuit
Other signals
6 – 17
CLKO
SDA,SDC
2
C
H,VSYNC
U Y V Y
ACL
STANDBY
Camera module side
DSP I/F
GX15
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