Toshiba Strata AirLink Installation Manual page 70

RWIU System Installation
RWIU Additional Information
o PHCLK - 2.048 MHz clock input
o 4MCLK - 4.096 MHz clock input
The interface with the voice channel has the following signals:
PCM matrix memory time switch device
o
o Digital I/O buffers (output enable)
The PHOUT connects to the matrix PCM input signal using a digital input buffer. The PHIN
connects to the output signal using a digital output buffer. It is enabled only during the
transmission phase of the data by the matrix. A time-slot assignment logic enables the output
buffer of the PHIN signal during the right time segment.
There are five hardwired address pins coming from the backplane connector (P1) of the RWIU and
one additional two-position DIP switch (S3). These are connected to seven input pins to control
the time-slot assignment logic for the various configurations. The CPU reads the status of these
hardwired addresses and the state of the two-position DIP switch (S3). An additional five-position
DIP switch (S2) selects various RWIU configurations and synchronizes the clock with the 8 KHz
frame synchronization pulse.
The receive data signal from the main PCM voice channel connects to input N0 (IN0) of the
matrix. The transmit data signal from the main PCM voice channel comes from output N0
(OUT0). The signal connects to a buffer that generates the external buffered transmit data signal
available on the backplane connector P1.
PCM busses generated by the matrix.
Table 19 Generated Internal Synchronous PCM Signal
PCM Bus
Number
1
2
3
4
60
Table 19
E1 Interface
RD01 internal synchronous PCM channel N1 receive data.
XDI1 internal synchronous PCM channel N1 transmit data
N1
signal, derived from input N1 (IN1) of the matrix while the
output signal is derived from output N1 (OUT1) of the
same matrix.
RD02 internal synchronous PCM channel N2 receive data.
XDI2 internal synchronous PCM channel N2 transmit data
N2
signal, derived from input N2 (IN2) of the matrix while the
output signal is derived from output N2 (OUT2) of the
same matrix.
RD03 internal synchronous PCM channel N3 receive data.
XDI3 internal synchronous PCM channel N3 transmit data
N3
signal, derived from input N3 (IN3) of the matrix while the
output signal is derived from output N3 (OUT3) of the
same matrix.
RD04 internal synchronous PCM channel N4 receive data.
XDI4 internal synchronous PCM channel N4 transmit data
N4
signal, derived from input N4 (IN4) of the matrix while the
output signal is derived from output N4 (OUT4) of the
same matrix.
describes the four internal synchronous 2.048
Signal
Strata AirLink Installation Guide 5/00