Sharp LC-32X20E Service Manual page 99

Ref No.
AK25
AL25
AM25
AN25
AP25
AK26
AL26
AM26
AN26
AP26
IEEE1394 Interface, 8051 and 656 share with 1394
AM7, AL7, AK7, AK8, AL8,
AM8, AK9, AL9
AM9
AM10
AL10
AK10
AM11
Transport Stream Interface
G4, G5, F1, F2, F3, F4, F5,
E5
G3
G2
G1
Pin Name I/O
VDB_R0 I/O Video input/output; Red channel bit 0;
IDE: IDE address bus bit 2.
EJTAG: PCST[8], output as EJTAG PC Trace bus, bit 8.
POD2: POD2_TS1_D1, the second POD_TS1 data[1].
VDB_R1 I/O Video input/output; Red channel bit 1;
IDE: IDE bus DMA acknowledge.
EJTAG: PCST[9], output as EJTAG PC Trace bus, bit 9.
POD2: POD2_TS1_D2, the second POD_TS1 data[2].
VDB_R2 I/O Video input/output; Red channel bit 2;
IDE: IDE bus IO Read Strobe signal.
EJTAG: PCST[10], output as EJTAG PC Trace bus, bit 10.
POD2: POD2_TS1_D3, the second POD_TS1 data[3].
VDB_R3 I/O Video input/output; Red channel bit 3;
IDE: IDE bus IO Write Strobe signal.
EJTAG: PCST[11], output as EJTAG PC Trace bus, bit 11.
POD2: POD2_TS1_D4, the second POD_TS1 data[4].
VDB_R4 I/O Video input/output; Red channel bit 4;
IDE: NOP
EJTAG:
S1=0, select DCLK/TPC[7:0]/PCST[11:0] of host CPU as output.
S1=1, select DCLK/TPC[7:0]/PCST[11:0] of slave CPU as output.
POD2: POD2_TS1_D5, the second POD_TS1 data[5].
VDB_R5 I/O Video input/output; Red channel bit 5;
IDE: NOP
EJTAG:
S1=0, two EJTAG are separately used.
S1=1, two EJTAG are used in a daisy chain style.
POD2: POD2_TS1_D6, the second POD_TS1 data[6].
VDB_R6 I/O Video input/output; Red channel bit 6;
IDE: NOP
EJTAG: TDI1, TDI EJTAG input of host CPU CPU.
POD2: POD2_TS1_D7, the second POD_TS1 data[7].
VDB_R7 I/O Video input/output; Red channel bit 7;
IDE: NOP
EJTAG: TDO1, TDO EJTAG input of host CPU CPU.
POD2: POD2_TS1_DEN, the second POD_TS1 data valid.
VDB_R8 I/O Video input/output; Red channel bit 8;
IDE: NOP
EJTAG: TMS1, TMS EJTAG input of host CPU CPU.
POD2: POD2_TS1_CLK, the second POD_TS1 clock.
VDB_R9 I/O Video input/output; Red channel bit 9;
IDE: NOP
EJTAG: TCK1, TCK EJTAG input of host CPU CPU.
POD2: POD2_TS1_SYNC, the second POD_TS1 SYNC.
HSD[7:0] I/O 1394: Parallel data.
Video 656 port; 656D[9:2], data[9:2]
8051: AD[7:0], AD bus.
HSDCLK I/O 1394: clock.
Video 656 port; 656CLK, clock.
8051: RD, ALE, address latch enable.
HSDRW I/O 1394: Not used.
Video 656 port; 656CHS, horizontal sync.
8051: RD, read signal, low active.
HSDSYNC I/O 1394: Packet synchronization.
Video 656 port; 656VS, vertical sync.
8051: WR, write signal, low active.
HSDAV I/O 1394: Not used.
Video 656 port; data[1].
8051: NOP
HSDEN I/O 1394: Data valid.
Video 656 port; data[0].
8051: CS, chip select.
TS2_D[7:0] I Transport Stream 2, data bus.
TS2_DEN I Transport Stream 2, data enable.
TS2_SYNC I Transport Stream 2, sync signal.
TS2_CLK I Transport Stream 2, clock.
LC-32X20E/S/RU, LC-37X20E/S/RU
Pin Function
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