Sharp LC-32X20E Service Manual page 87

2.9. IC3301 (RH-iXC010WJQZQ)
2.9.1 Pin Connections and short description
Pin No.
Ball Assignments for CPU Host Interface.
K20, K19, K18, K17, L20, A_D[7:0]
L19, L18, L17
M17, M18, M119, M20, ADDR[7:0]
N20, N19, N18, N17
J18 ALE
J19 WR#
J20 RD#
H17 SDA
H18 SCL
J17 CPU_CS
Ball Assignments for Analog Support Interface.
W1 XTALI
Y1 XTALO
U2 MLF1
R4 PLF2
Ball Assignments for Analog Input Interface.
Y4 CVBS1
V6 Y_G1
W6 Y_G2
Y6 Y_G3
W2 CVBS_OUT1
V2 CVBS_OUT2
V9 C
W9 PB_B1
Y9 PB_B2
Y10 PB_B3
Y8 PR_R1
W8 PR_R2
V8 PR_R3
W4, V4 FS2, FS1
U4, Y5 FB2, FB1
V10 AIN_H
U10 AIN_V
U8 PC_R
Y7 PC_G
W10 PC_B
Ball Assignments for Capture Interface (TV & RGB).
U18, U19, U20, T20, T18, DPB[15:8] (DP_B[15:8])
T17, R19, R20
Y12, U13, V13, W13, DPA[23:0] (DP_A[23:0])
Y13, Y14, W14, V14,
U14, U15, V15, W15,
Y16, W16, V16, U16,
U17, V17, W17, Y17,
Y18, W18, V18, W19
T19 DPB_CLK (CLK_B)
Y15 DPA_CLK (CLK_A)
W20 DPE_DE (DE_B)
Y20 DPA_VS (VS_A)
Y19 DPA_HS (HS_A)
V20 DPB_VS (VS_B)
V19 DPB_HS (HS_B)
P19 HS
P17 VS
Pin Name I/O
I/O Multiplexed address and data bus powered by VDDH/VSS.
I CPU Address. (Not connected)
I Address latch enables.
I CPU Write.
I CPU Read.
I/O I2C data.
I I2C clock.
I UX chip select pin from MCU. Active Low.
I Input for Clock Synthesizer. Supports 24MHz Oscillator or crystal powered by ana-
log PLL.
O Used in conjunction with XTALI for 24MHz crystal output powered by analog PLL.
I Low pass filter node for memory clock PLL powered by analog PLL.
I Low pass filter node for video clock PLL powered by analog PLL.
I Composite video input 1.
I Y input 1 of component or G input 1 of PC RGB.
I Y input 2 of component or G input 2 of PC RGB.
I Y input 3 of component or G input 3 of PC RGB.
I CVBS Output 1. (Not connected)
I CVBS Output 2. (Not connected)
I C input of S-Video.
I PB input 1 of component.
I PB input 2 of component.
I PB input 3 of component.
I PR input 1 of component.
I PR input 2 of component.
I PR input 3 of component.
I SCART function select 2, 1.
I SCART FB input for Port 2, Port 1.
I Hsync input (PC RGB input)
I Vsync input (PC RGB input)
I PC Red input.
I PC Green input.
I PC Blue INPUT.
I/O Digital input port [15:8] (Output reserved)
I/O Digital input/output port [23:0]
I/O Digital port B CLK input/output. (Not connected)
I/O Digital port A CLK input/output.
I/O DE input/output of Digital port B.
I/O Vsync input/output of Digital port A.
I/O Hsync input/output of Digital port A.
I/O Vsync input/output of Digital port B. (Not connected)
I/O Hsync input/output of Digital port B. (Not connected)
I/O Hsync output for Digital port.
I/O Vsync output for Digital port.
LC-32X20E/S/RU, LC-37X20E/S/RU
Pin Function
5 – 15