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LC-32X20E/S/RU, LC-37X20E/S/RU
1.11. IC1507 (VHiSii9185+-1Q)
Sil9185 is a 3-input/1-output switch compatible with HDMI1.3.
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Built in Consumer Electronics Control (CEC) support
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Individual control of Hot Plug Detect (HPD) for each port
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5V detect to help speed soft mute of audio during plug-in, plug-out conditions
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Control via local I2C bus.
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Supports video resolutions up to 1080p, 60Hz, 12-bit or 720p/1080i, 120Hz, 12-bit
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Built-in adaptive equalizer provides long cable support even at deep color resolutions
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Pre-emphasis in transmitter
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DVI 1.0, HDCP 1.1 and HDMI 1.3 compliant receiver and transmitter
1.12. IC9101 (RH-iXC121WJQZQ)
This IC performs the CPLD (Complex Programmable Logic Device) RESET, I/O and Bus control.
1.13. IC8101 (RH-iXC011WJQZQ)
HIDTVPro-LX Digital AV decoder & Main CPU.
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Master CPU with MMU.
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DDR2 memory up to 256mHz.
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Two Transport stream inputs, DVB compliant.
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Two HD MPEG2 video decoders.
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Demux, supports two TS inputs and one PS input.
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DVB_CI, up to two PCMCIA slots for CAM cards.
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DVB/DES.
AC3/MPEG2/MP3/AAC ⋅ ⋅ ⋅ audio.
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1920 x 1080p de-interlacing.
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Graphics engine.
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Two video planes and graphics planes with Alpha blender, overlay, scrolling, flashing, colour key, ARB support.
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Smart-Cards/UART/infrared IR/RTC/two HW timers/interrupt/Key button ADCs.
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Flash/IDE/PCI Host.
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Audio interface: AC97 link/I2S_out/I2S_in/SPDIF and lip-sync.
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Digital 24-bit RGB/YUV inputs.
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Dual port/Single port LVDS output.
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USB2.0 HOST/PHY built with EHCI.
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CVBS/S-video/YCbCr output.
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Two HD, 1920 x 1080p.
1.14. IC8701 (VHiS29GL128-1Q)
128Mbit Flash memory.
3.0V single power supply, page mode flash memory. It memorizes the program and broadcast data area.
1.15. IC8702 (RH-iXC150WJQZY)
The ICS275 field programmable VCXO clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference
clocks from a low-frequency crystal input. Using ICS' VersaClockTM software to configure PLLs and outputs, the ICS275 contains a One-Time Pro-
grammable (OTP) ROM for field programmability. Programming features include VCXO, eight selectable configuration registers and up to two sets of
two low-skew outputs.
Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock.
1.16. IC8301-4 (RH-iXC154WJQZQ)
4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM with Differential Data Strobe.
Program, DTV video buffer.
5 – 2
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