Y
OMEGANLF
ANTENNA
-i
ANALOG
k
fUVLF
INPUT
RCVR
L
t
I
DIGITAL DATA
DIGITAL
H
BUFFERED
CLK
PROCESSOR
RCVR
CONTROL
I
I
GND/OPEN
DISCRETE ~
DISCRETE
INPUTS
INTERFACE
HDGITAS
>
SYNCHRO
INPUTS
INTERFACE
TO
FMS
{r
DIGITAL
lNPUT/OUTPUT
4
RPU DC
28
VDC
*
POWER
'VOLTAGES REQUIRED
SUPPLY
212VDC
*
TOACU
AD-1 5927
02-800 Receiver Processor Unit
Block Diaqram
Figure
1~-2
22-14-00
Page 198.164
Apr 15/93
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