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MAINTENANCE
Honeywell !!RN!#&.
The A-processor has access to two presettable timers which it uses to set
the time base for the bus transactions (clock 1), and for the inner and
outer computational cycle in both processors (clock 2). The B-processor,
additionally, has a separate real time clock to time the servo loop
closure computational cycle (clock 3).
All the 1/0 is memory mapped.
Each processor individually controls its
own analog and discrete input/output transfers with the exception of the
serialized discretes. Discretes fall into two categories: direct and
serialized. The latching of the serialized discrete inputs is under the
control of the A-processor only.
Once the inputs are latched, however,
each processor has independent access to them. The serialized discrete
outputs (to the control panel) are solely under the control of the
A-processor.
The heartbeat monitor and power supply monitor interlocks ensure
disengagement of the FGC in case of a processor failure, a software
failure, a power supply failure or a power outage. The servo drive
engage interlocks ensure that the flight control functions can be
activated only if all the monitors are satisfied. The flight controls
are output through the trim, A/P and Y/D servo drives.
The flight director interface outputs the validity annunciations computed
by the A-processor.
The FGC digital outputs transmitted on the ASCB are listed in Table 7-2.
22-14-00
Page 198.40
Aug 15/91
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