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Advanced Chipset Setup,
BX Master Latency Timer (Clks) This option specifies the master latency timings (in PCI
clocks) for devices in the computer. The settings are Disabled, 32, 64, 96, 128,
160, 192, or 224. The Optimal and Fail-Safe default settings are 64.
Multi-Trans Timer (Clks) This option specifies the multi-trans latency timings (in PCI clocks)
for devices in the computer. The settings are Disabled, 32, 64, 96, 128, 160,
192, or 224. The Optimal and Fail-Safe default settings are 32.
PCI1 to PCI0 Access Set this option to Enabled to enable access between two different PCI
buses (PCI1 and PCI0). The settings are Enabled or Disabled. The Optimal and
Fail-Safe default settings are Enabled.
DRAM Integrity Mode This option sets the type of system memory checking. The settings are:
Setting
None
No error checking or error reporting is done.
ECC
Multibit errors are detected and reported as parity errors. Single-bit
errors are corrected by the chipset. Corrected bits of data from memory
are not written back to DRAM system memory. If Level I is selected, the
J25 External SMI software jumper on the Series 745 board is disabled.
ECC
Multibit errors are detected and reported as parity errors. Single-bit errors
Hardware
are corrected by the chipset and are written back to DRAM system
memory. If a soft (correctable) memory error occurs, writing the fixed
data back to DRAM system memory will resolve the problem. Most
DRAM errors are soft errors. If a hard (uncorrectable) error occurs,
writing the fixed data back to DRAM system memory does not solve the
problem. In this case, the second time the error occurs in the same
location, a Parity Error is reported, indicating an uncorrectable error. If
ECCI is selected, AMIBIOS automatically enables the System
Management Interface (SMI). If you do not want to enable power
management, set the Power Management/APM option to Disabled and
set all Power Management Setup timeout options to Disabled. To enable
power management, set Power Management /APM to Enabled and set
the power management timeout options as desired.
The Optimal and Fail-Safe default settings are ECC Hardware.
52
Olympus PCI Pentium II/Pentium III ISA Motherboard User's Guide
Continued
Description
Cont'd
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