Memory System - Sun Microsystems Sun Ultra 30 Service Manual

64-bit address pointers
16-Kbyte non-blocking data cache
16-Kbyte instruction cache with single cycle branch following
Power management
Software prefetch instruction support
Multiple outstanding requests
C.1.4

Memory System

The memory system (
uniprocessor plus (SC_UP+) ASIC, the crossbar switch 1 (UltraBMX) ASIC, and the
memory module. The SC_UP+ ASIC generates memory addresses and control
signals to the memory module. The SC_UP+ ASIC also coordinates the data transfers
among the DIMMs through the 144-bit-wide processor data bus (UPA_DATA0) and
the 72-bit-wide I/O data bus (UPA_DATA1).
DIMMs are organized in four rows with each row consisting of a bank 0 and a bank
1. DIMM capacities of 16 Mbytes, 32 Mbytes, 64 Mbytes, and 128 Mbytes are
supported by the memory module. When all DIMM slots are populated (16 DIMMs)
with 128-Mbyte DIMMs, maximum memory capacity is 2 gigabytes.
Organizing two DIMM banks of a given row with 128-Mbyte (plus ECC bit) DIMMs
allows data streams to be transferred on two 288-bit-wide (plus ECC) memory data
bus, designated MEM_DAT_A and MEM_DAT_B. The UltraBMX ASIC is controlled
by the SC_UP+ ASIC and performs all data bus switching.
) consists of three components: the system controller
FIGURE C-3
Appendix -7