Memory System - Sun Microsystems Ultra 80 Service Manual

Two graphics execution units
Selectable little- or big-endian byte ordering
64-bit address pointers
16-Kbyte non-blocking data cache
16-Kbyte instruction cache; single cycle branch following
Power management
Software prefetch instruction support
Multiple outstanding requests
C.1.5

Memory System

The system's motherboard provides sixteen slots for high-capacity dual inline
memory modules (DIMMs). Eight of the sixteen slots are located on the motherboard
and the other eight memory slots are located on the memory riser assembly. The
system supports Sun standard 168-pin, 5-volt, 60-nanosecond DIMMs. DIMMs of
16-, 32-, 64-, 128-, and 256-Mbyte capacities can be installed in the system, but only
DIMMs of 64- and 256-Mbyte capacities are supported. Total supported system
memory capacity ranges from 256 Mbytes to 4 Gbytes.
Memory slots are organized into four banks (bank 0 through bank 3), with each bank
comprising four slots. Each bank is divided between the motherboard and the
memory riser assembly. Consequently, the DIMMs must be installed in groups of
four, with two DIMMs being installed in a motherboard bank and the second set of
two DIMMs being installed in the associated memory riser assembly bank.The
system reads from, or writes to, all four DIMMs in a bank at the same time.
The memory system (see the following figure) consists of four components: the QSC
ASIC, the XB9++ ASIC, the CBT switching network, and the memory module.
The QSC ASIC generates memory addresses and control signals to the memory
module. The QSC ASIC also coordinates the two 288-bit-wide data bus {MEM_DAT0
and MEM_DAT1) data transfers between the XB9++ ASIC. Coordination is provided
by the BANK_SEL control signal to the CBT switching network.
The XB9++ ASIC exchanges 144-bit-wide bus data with the two CPU data buses:
UPA_DATA0 and UPA_DATA1; exchanges 64-bit-wide bus (UPA_E_DAT) data with
the two UPA graphic slots; and exchanges 72-bit-wide bus (UPA_D_DAT) data with
the U2P ASIC. This data is placed on a 576-bit-wide bus and exchanged with the
CBT switching network where it is divided on to two 276-bit-wide data buses and
exchanged with the memory module.
The following figure illustrates a functional block diagram of the memory system.
FIGURE C-4
FIGURE C-5
riser assembly.
illustrates the memory module arranged in four banks; 0, 1, 2, and 3.
shows the DIMM slot mapping for the motherboard and the memory
Appendix -9