Intel SE7520JR2 Technical Manual page 59

Intel® Server Board SE7520JR2
• Quick arbitrate and select (QAS)
• Skew compensation
• Inter-symbol interference (ISI) compensation
•
Cyclic redundancy check (CRC)
• Domain validation technology
The LSI53C1030 contains the following SCSI performance features:
• Supports Ultra320 SCSI
• Paced transfers using a free running clock
• 320 MB/s data transfer rate on each SCSI channel
• Mandatory packetized protocol
• Quick arbitrate and select (QAS)
• Skew compensation with bus training
• Transmitter precompensation to overcome ISI effects for SCSI data signals
• Retained training information (RTI)
• Offers a performance optimized architecture
• Three ARM966E-S processors provide high performance with low latency
•
Two independent Ultra320 SCSI channels
• Designed for optimal packetized performance
•
Uses proven integrated LVDlink transceivers for direct attach to either LVD or SE SCSI
buses with precision-controlled slew rates
• Supports expander communication protocol (ECP)
• Uses the Fusion-MPT (Message Passing Technology) drivers to provide support for
Windows*, Linux, and NetWare* operating systems
The LSI53C1039 has a 133 MHz, 64-bit PCI/PCI-X interface that supports the following PCI
features:
• Operates at 33 MHz or 66 MHz PCI
•
Operates at up to 133 MHz PCI-X
• Supports 32-bit or 64-bit data
• Supports 32-bit or 64-bit addressing through Dual Address Cycles (DAC)
• Provides a theoretical 1066 Mbytes/s zero wait state transfer rate
• Complies with the PCI Local Bus Specification, Revision 2.2
• Complies with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a
• Complies with the PCI Power Management Interface Specification, Revision 1.1
• Complies with the PC2001 System Design Guide
• Offers unmatched performance through the Fusion-MPT architecture
• Provides high throughput and low CPU utilization to off load the host processor
• Presents a single electrical load to the PCI Bus (True PCI Multifunction Device)
• Uses SCSI Interrupt Steering Logic (SISL) to provide alternate interrupt routing for RAID
applications
Revision 1.0
C78844-002
Functional Architecture
59