Intel SE7520JR2 Technical Manual page 185

Intel® Server Board SE7520JR2
FMC Signal Name
FML_SINTEX
FML_MDA_I2CSDA
ICH_LCLK
USB_M
FMM_SYSIRQ
USB_P
ICH_LAD1
FMM_RSMRST_N
ICH_LFRAME_N
ICH_LAD0
ICH_LAD3
ICH_LPCPD_N
ICH_LAD2
FMM_LPCRST_N
DFP_CLK
DFP_DAT
IPMB_I2C_5VSB_SDA
IPMB_I2C_5VSB_SCL
SMB_I2C_3VSB_SDA
SMB_I2C_3VSB_SCL
PERIPH_I2C_3VSB_SDA
PERIPH_I2C_3VSB_SCL
MCH_I2C_3V_SDA
MCH_I2C_3V_SCL
LAN_I2C_3VSB_SDA
Revision 1.0
FMC
Pin
27 Fast Management Link Slave Interrupt/Clock Extension. This signal is driven by
the FML Slave, and has a dual usage:
Used as an Alert signal for the slave to notify master that data is ready to be
read from slave
Used as a clock Extension (Stretching) for the slave to indicate to the master to
extend its low period of the clock
28 Fast Management Link Data Out. This signal is driven by the FML Master.
When not configured as FML, this signal is used as I2C data
31 LPC 33Mhz clock input
32 Reserved for future use as USB input. Baseboard can leave as NC
33 KCS interrupt signal from FMM Card.
34 Reserved for future use as USB input. Baseboard can leave as NC
35 LPC Address/data bus Bit 1
36 When this signal is asserted, the FMM is held in reset. This is a Standby reset
indication, and should be driven by a Standby monitor device such as the
Heceta7 or Dallas DS1815
37 LPC Cycle Framing
38 LPC Address/data bus Bit 0
39 LPC Address/data bus Bit 3
40 LPC Power down indication
41 LPC Address/data bus Bit 2
40 LPC bus reset. Must be properly buffered on motherboard to ensure
monotonicity
46 Serial clock signal for DFP EDID device. Must connect to DFP_CLK pin on the
graphics chip.
48 Serial data signal for DFP EDID device. Must connect to DFP_DAT pin on the
Graphics chip.
49 Connects to IPMB header
50 Connects to IPMB header
51 This bus should connect to the PCI slots, ICH, and mBMC (host I/F). An
isolated version of this bus (non-Standby) should connect to the DIMMs, and
clock buffer(s)
52 This bus should connect to the PCI slots, ICH, and mBMC (host I/F). An
isolated version of this bus (non-Standby) should connect to the DIMMs, and
clock buffer(s)
53 This bus should connect to the mBMC (Peripheral I/F), SIO, Heceta, Front panel
header. A level shifted version of this bus (5V Standby) should connect to the
Power Supply header
54 This bus should connect to the mBMC (Peripheral I/F), SIO, Heceta, Front panel
header. A level shifted version of this bus (5V Standby) should connect to the
Power Supply header
55 This bus should connect to the Northbridge and I/O bridge (MCH and PXH
respectively in the LH chipset). In a system that supports PCI Hot Plug, this bus
should also connect to the Power control devices if possible (such as the
MIC2591 for PCI-Express for example)
56 This bus should connect to the Northbridge and I/O bridge (MCH and PXH
respectively in the LH chipset). In a system that supports PCI Hot Plug, this bus
should also connect to the Power control devices if possible (such as the
MIC2591 for PCI-Express for example)
57 LAN usage
C78844-002
Connectors and Jumper Blocks
Description
185