Intel 80C186EA Preliminary Information page 26

16-bit high-integration embedded processors
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80C186EA 80C188EA 80L186EA 80L188EA
AC SPECIFICATIONS
AC Characteristics 80C186EA25 80C186EA20 80C186EA13
Symbol
Parameter
SYNCHRONOUS INPUTS
T
TEST NMI INT3 0
CHIS
T1 0IN ARDY
T
TEST NMI INT3 0
CHIH
T1 0IN ARDY
T
AD15 0 (AD7 0) ARDY
CLIS
SRDY DRQ1 0
T
AD15 0 (AD7 0) ARDY
CLIH
SRDY DRQ1 0
T
HOLD PEREQ ERROR
CLIS
(80C186EA Only)
T
HOLD PEREQ ERROR
CLIH
(80C186EA Only)
T
RESIN (to CLKIN)
CLIS
T
RESIN (from CLKIN)
CLIH
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measured at V
for high time V
IH
3 Only required to guarantee I
CC
4 Specified for a 50 pF load see Figure 13 for capacitive derating information
5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF
6 See Figure 14 for rise and fall times
7 T
applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
CHOV1
8 T
applies to RD and WR only after a HOLD release
CHOV2
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
11 T
applies to BHE (RFSH) and A19 16 only after a HOLD release
CHOVS
12 Operating conditions for 25 MHz are 0 C to
Pin names in parentheses apply to the 80C188EA 80L188EA
26
(Continued)
Min
Max
(12)
25 MHz
8
3
10
3
10
3
10
3
for low time
IL
Maximum limits are bounded by T
70 C V
a
e
CC
Min
Max
Min
Max
20 MHz
13 MHz
10
10
3
3
10
10
3
3
10
10
3
3
10
10
3
3
T
and T
C
CH
CL
5 0V
10%
g
Units
Notes
ns
1 9
ns
1 9
ns
1 10
ns
1 10
ns
1 9
ns
1 9
ns
1 9
ns
1 9
26

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