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80C186EA 80C188EA 80L186EA 80L188EA
DC SPECIFICATIONS (80C186EA 80C188EA)
Symbol
Parameter
V
Supply Voltage
CC
V
Input Low Voltage for All Pins
IL
V
Input High Voltage for All Pins
IH
V
Output Low Voltage
OL
V
Output High Voltage
OH
V
Input Hysterisis on RESIN
HYR
I
Input Leakage Current (except
IL1
RD QSMD UCS LCS MCS0 PEREQ
MCS1 ERROR LOCK and TEST BUSY)
I
Input Leakage Current
IL2
(RD QSMD UCS LCS MCS0 PEREQ
MCS1 ERROR LOCK and TEST BUSY
I
Output Leakage Current
OL
I
Supply Current Cold (RESET)
CC
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
I
Supply Current In Idle Mode
ID
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
I
Supply Current In Powerdown Mode
PD
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
C
Output Pin Capacitance
OUT
C
Input Pin Capacitance
IN
NOTES
1 RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY have internal pullups that are only acti-
vated during RESET Loading these pins above I
operation
2 Output pins are floated using HOLD or ONCE Mode
3 Measured at worst case temperature and V
device in RESET (RESIN held low) RESET is worst case for I
4 Output capacitance is the capacitive load of a floating output pin
5 Operating conditions for 25 MHz are 0 C to
22
Min
4 5
0 5
b
0 7 V
V
CC
V
0 5
b
CC
0 30
275
b
0
0
275
A will cause the processor to enter alternate modes of
e b
OL
with all outputs loaded as specified in the AC Test Conditions and with the
CC
CC
70 C V
5 0V
10%
a
e
CC
g
Max
Units
Conditions
5 5
V
0 3 V
V
CC
0 5
V
a
CC
0 45
V
I
3 mA (min)
e
OL
V
I
e b
OH
V
10
A
0V
V
s
IN s
g
A
V
0 7 V
e
IN
(Note 1)
0 45
V
s
10
A
g
(Note 2)
105
mA
(Notes 3 5)
90
mA
65
mA
90
mA
(Note 5)
70
mA
46
mA
100
A
(Note 5)
100
A
100
A
15
pF
T
1 MHz (Note 4)
e
F
15
pF
T
1 MHz
e
F
2 mA (min)
V
CC
CC
V
OUT s
CC
22
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