SOYO SY-7ISA User Manual page 73

BIOS Setup Utility
CHIPSET FEATURES SETUP
CHIPSET Setting
FEATURES
System BIOS Disabled
Cacheable
Enabled
Disabled
Video BIOS
Cacheable Enabled
Memory Disabled
Hole At 15M-
Enabled
16M
CPU Latency Disabled
Timer
Enabled
Delayed Disabled
Transaction
Enabled
AGP 64MB
Graphics
4MB,
Aperture
8MB,
Size
16MB,
32MB,
128MB,
256MB
Disabled
Use VGA
BIOS in VBU
Enabled
Block
Description
The ROM area F0000H-FFFFFH is
cacheable.
The video BIOS C0000H-C7FFFH is
cacheable.
Some interface cards will map their
ROM address to this area. If this
occurs, select [Enabled] in this field.
When enabled this item, the CPU
cycle will only be deferred after it has
been held in a "Snoop Stall" for 31
clocks and another ADS# has arrived.
When disabled, the CPU cycle will be
deferred immediately after the GMCH
receives another ADS#.
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled to
support compliance with PCI
specification version 2.1.
Select the size of Accelerated Graphics
Port (AGP) aperture. The aperture is a
portion of the PCI memory address
range dedicated for graphics memory
address space. Host cycles that hit
the aperture range are forwarded to the
AGP without any translation.
If you do not make use of the onboard
VGA function you can set this item to
disabled, this way the VGA BIOS will
not be copied into the bootblock.
69
SY-7ISA
Note
Default
Default
Default
Default
Default
Default