Sharp UP-600 Service Manual page 53

6. INTERFACE WITH HOST CPU
1) SIGNAL LINES
The following signal lines are required for the interface with the host CPU.
Signal name I/O
A0~A11 I Address Bus from host CPU
D0~D7 I/O Data Bus from host CPU
/RD I Read signal from host CPU
/WR I Write signal from host CPU
/DPCS I Chip select from host CPU
/LRES I Rest signal for this board from host CPU
/INTSR O Data read end interrupt from board CPU
/INTSW O Data write end interrupt from board CPU
A13~A15 I Address bus from host CPU (for decode)
Vcc Power(+5V)
GND GND
Signals prefixed with a slash "/" are active in low level.
Cautions to be taken when designing the host side
1. It is preferable that /LRES signal to be input into the board can
also be controlled by software.
2. The access timing satisfies the dual-port SRAM specification.
•
Timing Waveform of Read Cycle No. 1, Either Side
t
RC
ADDRESS
(5)
t
AA
t
OH
DATA PREVIOUS DATA VALID
OUT
•
Timing Waveform of Read Cycle No. 2, Either Side
t
ACE
CE
t
AOE
OE
(1)
t
LZ
DATA
OUT
(1)
t
LZ
t
PU
ICC
50%
CURRENT
I
SB
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective,
tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address
Access.
Description
(1,2,4)
t
OH
DATA VALID
(1,3)
(4) (2)
t
HZ
(2)
t
HZ
(4)
VALID DATA
t
PD
50%
Connected to
DP-RAM
DP-RAM
DP-RAM
DP-RAM
DP-RAM
Board CPU
LOGIC
LOGIC
LOGIC
•
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
ADDRESS
(6)
t
AS
OE
t
AW
CE
R/W
(7)
t
WZ
(7)
t
LZ
DATA (4)
OUT
DATA
IN
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and
R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to
the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input
signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the
R/W = VIL transition, the outputs remain in the High-impedance
state.
6. Timing depends on which enable signal (CE or R/W) is asserted
last.
7. This parameter is guaranteed by device characterization, but is
not production tested. Transition is measured
steady state with the Output Test Load (Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse
width must be the larger of tWP or (tWZ + tDW) to allow the I/O
drivers to turn off data to be placed on the bus for the required
tDW. If OE = VIH during an R/W controlled write cycle, this re-
quirement does not apply and the write pulse can be as short as
the specified tWP.
Connection pin
A0R~A11R
D0R~D7R
/OER
R/WR
/CER
/RES
(1,5,8)
t
WC
(3)
t
WR
(7)
t
HZ
(2)
t
WP
t (7)
HZ
t
OW
(4)
t
DH
t
DW
500mV from