Sharp UP-600 Service Manual page 43

1) CPU INTERFACE
The figure below shows a typical pseudo SRAM interface in the UP-
600.
S RAM(Standard)
A0~A18
A0~A18
D0~D7
/RD
/WR
/CE
S RAM(Option)
A0~
A18
74LV138
A19~
A21
A,B,C
Y
/G
2) SRAM ADDRESS
Standard SRAM is decoded as follows by the RASPN1 signal.
780000h ∼ 7FFFFFh
The base signal is 2MB. It thus wraparounds with 600000H ∼
7FFFFFH 1.5MB.
7. NOR-type FLASH MEMORY
Here is the explanation for the interface of NOR-type flash memory.
The device is Sharp's LH28F016SU flash memory which consists of
512 K words × 16 or 1 MB × 8, with 32 blocks of 64 KB.
1) CPU INTERFACE
The figure below shows a typical interface for the LH28F016SU of the
UP-600 system.
DATA
ADDRES
H8/510 HWR-
RD-
FVPON
PORT64
NORDY
PORT63
RESET-
MPCA8
FROS1-
2) DEVICE CONTROL
After resetting, the device automatically enters the array read mode
and performs the same action as the usual ROM, thus requiring no
special consideration when reading data.
Data can be written at a high speed by using the page buffer.
A0~A21
D8~D15
MPCA9
/RD
/HWR
/RESET
RASPN1
RASPN2
5V
DQ0~DQ1
VCC
VPP
A0~A2
WE#
OE# LH28F
016SUT
WP#
RY/BY#
RP#
BYTE#
CE0#
3/5#
CE1#
GND
8. SSP CONTROL
The UP-600 uses flash memory in the place of EPROM, so it is
possible to rewrite the contents of the flash memory in changing the
program. However, since the existing gate array MPCA8 is used, it is
also possible to use the conventional SSP.
1) OPERATION
Like the MPCA5 ~ 8, the MPCA9 adopts the break address register
comparison method for detecting addresses. The operation of this
method is briefly explained below.
The gate array always compares the break address register (BAR)
built in the gate array, with the address bus to monitor the address
bus.
If both agree, the gate array outputs the NMI signal to the CPU, which
in turn shifts from normal handling to exception handling.
In both the MPCA5 ~ 8 and the MPCA9, SSP is achieved by the
above operation.
The setting of the break address register (BAR) is directly written in
the addresses from FFFF00h to FFFFFFh.
9. INTERRUPT CONTROL
There are roughly two types of interrupts:
•
Internal interrupts: Controlled inside the CPU
•
External interrupts: Input into the CPU from outside
1) INTERNAL INTERRUPTS
Device interrupts built in the CPU are used for the following applica-
tions:
Event factor
SC11 Interrupt source as RS232 : CH8
SC12 Not used (SC1 is used for CKDC interface.)
INTMCR ∼ MCR interrupt (to FT11 terminal)
FRT1 (ICI)
(OCRA)
(OCRB)
(OVF)
FRT2 (ICI) Standard SHEN event (for CKDC)
(OCRA) Simple IRC timer event
(OCRB) RS232 timer event
(OVF) System timer (53 ms)
TMR (CMA)
(CMB)
(OVF)
WDT (OVF) Drawer open timer
A/D Not used
NMI SSP request
2) EXTERNAL INTERRUPTS
The following types of external interrupts are available:
•
NMI (SSP)
•
IRQ0 (Standard I/O interrupt)
•
IRQ1 (RS232 interrupt)
•
IRQ2 (Not Used)
•
IRQ3 (Used as SCK terminal)
Application