Sharp UP-600 Service Manual page 41

3. ADDRESS MAP
1) TOTAL MEMORY SPACE
The address map of the total memory space is shown below. As you
can see, the memory space is divided into the following 5 blocks:
0page area (including the I/O area)
•
VRAM
•
RAM
•
ROM
•
Extended I/O area
000000h
0 page area
(64KB)
00FFFFh
200000h
Flash
(4MB)
600000h
STD RAM (2MB)
800000h
EXTEND RAM
(4MB)
C00000h
VRAM (128KB)
C20000h
D00000h
EP-ROM
(2MB)
F00000h
Extended I/O area
(1MB)
FFFFFFh
* In the 0 page area, lower 64KB
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
* The expanded I/O area means
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.
2) 0PAGE AREA
The 0page area consists of four spaces: the ROM mapped area,
internal and external I/O areas.
The ROM mapped area has been devised for the following purposes:
Simplifying the procedure for booting the IPL program
Achieving high-speed accessing, and accessing by abbreviated
instructions.
000000h
ROM mapping area
00FE80h
Internal I/O area
00FF80h
External I/O area
00FFFFh
3) I/O AREAS
The addresses from 00FF80h to 00FFFFh are called the internal I/O
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
00FE80h
Internal I/O area
00FF80h
MPCCS
00FFA0h
Expanded MPC
(not used)
00FFB0h
MCR1Z
00FFB4h
MCR2Z
00FFB8h
T/PZ
00FFBCh
MCR3Z
00FFC0h
OPCCS1
00FFD0h
OPCCS2
00FFE0h
CPCSZ (not used)
00FFF0h
TPRC1
00FFFFh
* The ROM area 200000h to
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
* The internal I/O area is used
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
I/O area
* MPCCS and expanded MPC
signals are base signals for
MPCA9 internal register
decode. There is no external
signal.
* MCR1Z and MCR2Z are chip
* MCR1Z, MCR2Z and MCR3Z
are chip select signals for the
magnet card reader.
(Use lower 2bytes.)
* T/PZ is the internal decode
signal for USART built in
MPCA9. Thereis no external
signal. (Use lower 2bytes.)
* OPCCS1 and OPCCS2
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
OPTCSZ
* CPCSZ is CPC select for
Centronics Interface.
TPRC1 is built in by
MPCA9.