LG KG195 Service Manual page 55

4. Circuit Description
4.2.19.2 Transmitter
The MT6129 transmitter section consists of two on-chip TX VCOs, buffer amplifiers, a down-converting
mixer, a quadrature modulator, an analog phase detector (PD) and a digital phase frequency detector
(PFD), each with a charge pump output and on chip loop filter.
The dividers and loop filters are used to achieve the desired IF frequency from the downconversion
mixer and quadrature modulator. For a given transmission channel, the transmitter will select one of the
two different TX reference dividing numbers. These built-in components, along with an internal voltage
controlled oscillator (TX VCO) and a loop filter, implement a translation loop modulator. The TX VCO
output is fed to the power amplifier (PA). A control loop, implemented externally, is used to control the
PA's output power level.
4.2.19.3 TX VCO
Two power VCOs are integrated with OPLL to form a complete transmitter circuit. The TX VCO output
power is typically 9 dBm with +/- 2.5dB variation in E-GSM900/ GSM850 bands and +8 dBm output
powers with +/- 2dB variation in DCS1800/ PCS1900 bands over extreme temperature conditions.
Inside the chip, the VCO differential output signals are fed into the output buffer, the OPLL input
feedback buffer, and the calibration circuit. The off chip signal is transformed into a single ended output
which needs impedance matching to 50_to drive the power amplifier. Like RF VCO, the oscillation
bandwidth is partitioned into 128 (or 64) sub-bands for DCS/ PCS (for E-GSM900/ GSM850) TX VCO
to cover the process and temperature variation. Calibration process begins after a period of
programmable time when the on chip TX VCO regulator is turned on. Total calibration time needs about
60us maximally and the frequency error after calibration is within +/-5 MHz. For Vtune = 1.2 V, the
variation of kvco is about 14% and 40% for GSM and DCS/PCS TX VCO, respectively, across the
desired frequency range.
4.2.19.4 Frequency Synthesizer
The MT6129 includes a frequency synthesizer with a fully integrated RF VCO to generate RX and TX
local oscillator frequencies. The PLL locks the RF VCO to a precision reference frequency at 26 MHz.
In order to reduce the inherent spur caused by fractional-N synthesizers, a 3rd-order sigma-delta
modulator with dithering function is used to generate the prescaler divider number N. The prescaler is
based on a multi-modulus architecture with programmable divider numbers ranging from 64 to 127. A
conventional digital-type PFD with a charge pump is used for phase comparison in the PLL. By
changing the output current of the charge pump, the phase detector gain can be programmed from75/_
_A/rad to 600/_ _A/rad.
To reduce the acquisition time or to enable fast settling time for multi-slot data services such as GPRS,
a digital loop (calibration loop) along with a fast-acquisition system are implemented in the synthesizer.
Once the synthesizer is programmed, the RF VCO is preset to the vicinity of the desired frequency by a
digital calibration loop. After the calibration, a fast-acquisition system is utilized for a period of time to
facilitate fast locking. Once the acquisition is done, the PLL reverts back to the normal operation mode.
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