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1. PIN ASSIGNMENT (TOP VIEW)
2. Pin List
PIN NAMES
A0 to A22
Address inputs for Pseudo SRAM & Nor Flash Memory
DQ0 to DQ15
Data inputs / outputs for Pseudo SRAM & Nor Flash Memory
I/O1 to I/O8
Data inputs / outputs for Nand E
, CE2ps
Chip enable inputs for Pseudo SRAM
CE1ps
Chip enable inputs for Nor Flash Memory
CEf
Chip enable inputs for Nand E
CEn
Output enable input for Pseudo SRAM & Nor Flash Memory
OE
Write enable input for Pseudo SRAM & Nor Flash Memory
WE
Read enable input for Nand E
REn
Write enable input for Nand E
WEn
Data byte control input for Pseudo SRAM
LB, UB
CLE
Command latch enable input for Nand E
ALE
Address latch enable input for Nand E
Write protect/program acceleration input for Nor Flash Memory
WP/ACC
Write protect input for Nand E
WPn
Hardware reset input for Nor Flash Memory
RESET
Ready/Busy output for Nor Flash Memory
RY/BYf
Ready/Busy output for Nand E
RY/BYn
V
Power supply for Pseudo SRAM
CCps
V
Power supply for Nor Flash Memory
CCf
V
Power supply for Nand E
CCn
V
Ground
SS
NC
Not connected
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
FLASH MEMORY
2
PROM
2
PROM
2
PROM
2
PROM
2
PROM
2
PROM
2
PROM
2
PROM
2
PROM
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7. Device Information
LGE Internal Use Only
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