JVC TH-A5 Service Manual page 31

CS8415A (DIC14) : Digital audio receiver
1. Pin layout
SDA/CDOUT 1 28
AD0/CS 2 27
EMPH 3 26
RXP0 4 25
RXN0 5 24
VA+ 6 23
AGND 7 22
FILT 8 21
RST 9 20
RMCK 10 19
RERR 11 18
RXP1 12 17
RXP2 13 16
RXP3 14 15
3. Block diagram
VA+ AGND
Receiver
RSN0
RXP6
RXP5
RXP4
7:1
RXP3
MUX
RXP2
RXP1
RXP0
2. Pin function
Pin No. Symbol
SCL/CCLK
1 SDA/CDOUT
AD1/CDIN
RXP6
2 AD0/CS
RXP5
3
H/S
4
VD+
5
DGND
6
OMCK
7
U
INT
8
SDOUT
9
OLRCK
10
OSCLK
11
RXP4
12,13 RXP1,RXP2
14,15 RXP3,RXP4
25,26
RXP5,RXP6
16 OSCLK
17 OLRCK
18 SDOUT
19
20
21
22
23
24
27 AD1/CDIN
28 SCL/CCLK
FILT RERR RMCK
Clock &
Data
Recovery
Misc.
Control
H/S RST
EMPH U
I/O
I/O Serial Control Data I/O(I2C) / Data Out(SPI)
I/O Address Bit 0(I2C) / Control Port Chip Select(SPI)
EMPH O Pre-Emphasis
AES3/SPDIF Receiver Power
RXP0 I
RXN0
VA+ I Positive Analog Power
AGND I Analog Ground
FILT O PLL Loop Filter
Reset
RST O
RMCK I/O Input Section Recovered Master Clock
RERR O Receiver Error
I Additional AES3/SPDIF Receiver Port
I/O Serial Audio Output Bit Clock
I/O Serial Audio Output Left/Right Clock
O Serial Audio Output Data
Interrupt
INT O
U O User Data
OMCK I System Clock
DGND I Digital Ground
VD+ I Positive Digital Power
Hardware/Sofrware Mode Control
H/S I
I Address Bit 1(I2C) / serial Control Data in (SPI)
I Control Port Clock
VD+ DGND
AES
C&U bit
S/PDIF
Data
Buffer
Decoder
Control
Port &
Registers
SCL/ AD1/
SDA/
CCLK CDIN
CDOUT
Function
OMCK
Serial
OLRCK
Audio
OSCLK
Output
SDOUT
AD0/ INT
CS
TH-A5
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