JVC TH-A5 Service Manual page 28

TH-A5
SST39VF800A (U6) : 8M Flash memory
1. Pin layout
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
NC 10
WE# 11
NC 12
NC 13
NC 14
NC 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
2. Block diagram
Memory Address
CE#
OE#
WE#
3. Pin function
Symbol Pin name
AMS- A0 Address Inputs
DQ15- DQ0 Data Input/Output
CE# Chip Enable
OE# Output Enable
WE# Write Enable
VDD Power Supply
Vss Ground
NC No Connection
1-28
X-Decoder
Address Buffer & Latches
Control Logic
To provide memory addresses. During Sector-Erase AMS-A11 address lines will
select the sector. During Block-Erase AMS-A15 address lines will select the block.
To output data during Read cycles and receive input data during Write cycles. Data is
internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is
high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
Unconnected pins.
48 A16
47
NC
46 Vss
45
DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40
DQ5
39 DQ12
38
DQ4
37 VDD
36
DQ11
35 DQ3
34
DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29
DQ0
28 OE#
27
Vss
26 CE#
25
A0
I/O Buffers & Data Latches
Function
EEPROM
Cell Array
Y-Decoder
DQ15-DQ0