JVC TH-A5 Service Manual page 30

TH-A5
74VHCT244A (DIC12) : Buffer/Line driver
1. Pin layout
OE1 1
I0 2
O4 3
I1 4
O5 5
I2 6
O6 7
I3 8
O7 9
GND 10
74LVT573 (U10, U11, U12) : Latch
1. Pin layout
OE 1 20
D0 2 19
D1 3 18
D2 4 17
D3 5 16
D4 6 15
D5 7 14
D6 8 13
D7 9 12
GND 10 11
MM74HCT245 (U15) : Transceiver
1. Pin layout
ENABLE
Vcc G B1 B2 B3
20 19 18 17 16
1 2 3 4 5
DIR A1 A2 A3 A4
1-30
20 Vcc
19 OE2
18 O0
17 I4
16 O1
15 I5
14 O2
13 I6
12 O3
11 I7
2. Pin function
Function
Symbol
Vcc
O0
D0-D7 Data Inputs
O1
LE Latch Enable Input
O2
O3 Output Enable Input
OE
O4
O0-O7 3-STATE Latch Outputs
O5
O6
O7
LE
B4 B5 B6 B7 B8
15 14 13 12 11
6 7 8 9 10
A5 A6 A7 A8 GND
2. Pin function
Symbol Function
OE1,OE2 3-STATE Output Enable Inputs
I0-I7 Inputs
O0-O7 3-STATE Outputs
3. Truth table
Inputs
Outputs
(Pins12,14,16,18)
OE1 In
L L
L H
H X
Inputs
Outputs
(Pins3,5,7,9)
OE2 In
L L
L H
H X
H:HIGH Voltage Level
L:LOW Voltage Level
I:Immaterial
Z:High Impedance
2. Truth table
Control
Operation
Inputs
G DIR 245
L L B data to A bus
L H A data to B bus
H X isolation
H=HIGH Level
L=LOW Level
X=Irrelevant
L
H
Z
L
H
Z
3. Truth table
Inputs
LE OE Dn
X H X
H L L
H L H
L L X
H:HIGH Voltage Level
L:LOW Voltage Level
Z:High Impedance
X:Immaterial
O0:Previous O0 before HIGH to LOW transition of Latch Enable
Outputs
On
Z
L
H
O0