Sony STR-DA7100ES Service Manual page 38

STR-DA7100ES
DIGITAL BOARD IC2054 MB91F355APMT-A70ES-X110 (MAIN SYSTEM CONTROLLER)
Pin No. Pin Name
BASS JOG1,
1, 2
BASS JOG2
TREB JOG1,
3, 4
TREB JOG2
5 SVOL LAT (A90)
6 TUNER LAT
7 TUNER DO
8 TUNED
9 STEREO
10 RDS DATA
11 DATA0
12 DSP RESET
13 DSP (LAT)
14 DSP SPICLK
15 DSP MISO
16 DSP MOSI
17 VSS
18 VCC
DSP BCFG0,
19, 20
DSP BCFG1
21 SF CPU CE
22 SF DSP MAS
23 96/24
24 T/A XCS
25 T/A SO
26 T/A XRST
27 MAIN DO
28 MAIN CLK
29 SUB-U RESET
30 DIR XMODE
31 DIR CE
32 DIR DO
33 DIR ERROR
34 DIR CKST
35 VSS
36 VCC
37 AD/DA RESET
38 DAC LAT
39 DAC OUT
40 AD (SB) RESET
41 ADMIX LAT (A90)
42 PDMIX LAT (A90)
43 RF ERR (A90)
44 MUTE
45 DAVS
46 DAVC
47 to 49 NO USE
50 to 52 AD KEY1 to AD KEY3
53, 54 NO USE
38
I/O
I Jog dial pulse input from the rotary encoder (for BASS)
I Jog dial pulse input from the rotary encoder (for TREBLE)
- Not used
O Serial data latch pulse signal output to the tuner unit
I Serial data input from the tuner unit
I Tuned detection signal input from the tuner unit
I FM stereo detection signal input from the tuner unit
I RDS serial data input from the tuner unit (AEP model only)
I Read data input from the digital audio interface receiver
O System reset signal output to the DSP "L": reset
O Serial data latch pulse output to the DSP
O Serial data transfer clock signal output to the DSP
I Serial data input from the DSP or flash memory
O Serial data output to the DSP or flash memory
- Ground terminal
- Power supply terminal (+3.3V)
- Not used
O Chip enable signal output for the flash memory
I Master/slave selection signal input terminal "H": DSP is master
- Not used
O Chip select signal output to the lip sync adjust
I Serial data input from the lip sync adjust
O System reset signal output to the lip sync adjust "L": reset
O Serial data output to the PCM/PWM processor
O Serial data transfer clock signal output to the PCM/PWM processor
O System reset signal output to the sub system controller "L": reset
O System reset signal output to the digital audio interface receiver "L": reset
O Chip enable signal output to the digital audio interface receiver
I Serial data input from the digital audio interface receiver
I PLL lock error signal and data error flag input from the digital audio interface receiver
I Clock select signal input from the digital audio interface receiver
- Ground terminal
- Power supply terminal (+3.3V)
O System reset signal output to the A/D converter and D/A converter "L": reset
O Serial data latch pulse signal output to the D/A converter
I Serial data input from the D/A converter
O System reset signal output to the A/D converter (for surround back) "L": reset
- Not used
- Not used
- Not used
O System muting on/off control signal output terminal
- Ground terminal
- Power supply terminal (+3.3V)
- Not used
I Front panel key input terminal (A/D input)
- Not used
Description