Pll Circuits; Antenna Tuner Circuits; 1St Lo Pll Circuit (Main Unit); Antenna Matching Network Circuit - Icom IC-703 Service Manual

(2) ALC meter
The ALC bias voltage from IC2701 pin 14 is applied to the
main CPU (IC5901) via the "ALCV" signal line for indicating
the ALC level.
(3) SWR meter
The "FORL" and "REFL" voltages are applied to the main
CPU (IC5901) via the A/D converter (IC5601, pins 12 and 1)
respectively. The main CPU compares the ratio of "FORV" to
"REFV" voltage and indicates the SWR for the [ANT] con-
nector.

3-3 PLL CIRCUITS

3-3-1 GENERAL
The PLL circuits generates a 1st LO frequency
(64.485–124.455 MHz), a 2nd LO frequency (64 MHz), a
BFO frequency (455 kHz).
The 1st LO PLL circuit adopts a mixer-less dual loop PLL
system and has 2 VCO circuits. The BFO uses a DDS and
the 2nd LO uses a 64 MHz fixed frequency.

3-3-2 1ST LO PLL CIRCUIT (MAIN UNIT)

The 1st LO PLL contains a main loop and reference loop
forming a dual loop system.
The reference loop generates a 6.5 MHz frequency using a
DDS circuit, and the main loop generates a 64.485 to
124.455 MHz frequency using the reference loop frequency.
(1) REFERENCE LOOP PLL
The oscillated signal at the reference passes through the
low-pass filter (L9521, L9523, C9521–C9526), and is then
amplified at the amplifier (IC9521). The amplified signal is
applied to the DDS IC (IC9001, pin 5) via the low-pass filters
(L9524, L9525, C9528–C9530,
C9023–C9025). The signal is then divided and detected on
phase with the DDS generated frequency.
The detected signals output from IC9001 (pin 10) are ampli-
fied at the buffer amplifier (Q9051), and then pass through
the band-pass filter (L9051–L9053, C9053–C9056) to sup-
press spurious components. The signal is applied to the PLL
IC (IC9101, pin 1) as PLL lock voltage.
(2) MAIN LOOP PLL
The oscillated signal at one of the main loop VCOs (HF:
Q9201, 50 MHz: Q9251) is amplified at the buffer amplifier
(Q9301) and is then applied to the PLL IC (IC9101, pin 4).
The signal is then divided and detected on phase with the
reference loop output frequency.
The detected signal output from the PLL IC (IC9101, pin 13)
is converted into a DC voltage (lock voltage) at the active
loop filter and then fed back to one of the varactor diodes
(D9201, D9251) in the VCO circuits
The oscillated signal passes through a low-pass and high-
pass filters, and is then applied to the 1st mixer (D701) as a
1st LO signal.
3-3-3 2ND LO AND REFERENCE OSCILLATOR
The reference oscillator (IC9601, Q9621, X9501) generates
a 64 MHz frequency used for the 2nd LO signal.
The oscillated signal is amplified at the buffer amplifier
(Q9651), and is then passed through the low-pass filter
(L9672, C9673, C9675) to suppress the high harmonics
components. The filtered 64 MHz signal is applied to the 2nd
mixer (D901) via the 3 dB attenuator (R9672–R9674) as a
2nd LO signal.
3-3-4 BFO CIRCUIT (MAIN UNIT)
The DDS IC (IC9701) generates a 455 kHz BFO signal. The
signa is passed through the low-pass filter (L9751, C9753,
C9754, C9756) to suppress high harmonics suprious com-
ponents. The 455 kHz BFO signal is then applied to the SSB
detector (IC1901, pin 3) and SSB modulator (IC1801, pin 1)
via the "BFO" signal line.
While transmitting in RTTY mode, the RTTY keying signal is
applied to IC9701 to shift the generated frequency and to
obtain 2 frequencies for FSK operation.
CW receiving pitch control, RTTY receiving tone, RTTY
transmitting mark are controled by changing BFO frequency.

3-4 ANTENNA TUNER CIRCUITS

3-4-1 ANTENNA MATCHING NETWORK CIRCUIT

The antenna tuner circuit consists of the antenna matching
network circuit, SWR detector circuit, impedance detector
circuit, phase detector circuit, etc.
When antenna tuning is ON, the antenna matching network
circuit switches ON via the RL640 and RL641.
The attenuator's impedance is set to 50 Ω which is same as
L9021, L9022,
power amplifier's output impedance. The attenuator's input
impedance is about SWR 1, however its output impedance
changes variably. Therefore, attenuator's output impedance
is matched to the antenna to become about SWR 1, then
impedance matching is depended on input impedance. The
antenna matching network circuit switches OFF via the
RL640 and RL641 when the impedance is matched between
the output impedance and antenna.
The antenna matching network circuit is composed between
RL640 and RL641. Therefore, each detecting circuits work
when antenna tuning is ON only. Thus, There isn't influence
about loss of each detecting circuits when antenna tuning is
OFF. In addition, the output power from the power amplifier
(Q200, Q201) is applied to the this circuit as low power via
the attenuator. Therefore, the output power doesn't effect to
interference while impedance tuning.
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CIRCUITS (MAIN UNIT)
(PA UNIT)