Signal Descriptions - Harman Kardon AVR145 Service Manual

5 x 40w 5.1 channel a/v receiver
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AVR145
M29W800DT, M29W800DB

SIGNAL DESCRIPTIONS

See
Figure
1., Signal
Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A18). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V
. When BYTE is Low, V
IH
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-
1). When BYTE is High, V
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
, all other pins are ignored.
IH
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory's Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, V
IH
Read and Bus Write operations after t
10/42
2., Logic
Diagram,
and
, these pins
IL
, this pin behaves as
IH
, this pin behaves as an address
IL
, for at least
IL
, the memory will be ready for Bus
Table
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section,
Block Temporary Unprotect AC
more details.
Holding RP at V
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
.
PHPHH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See
Block Temporary Unprotect AC Characteristics
and
Figure 15., Reset/Block Temporary Unprotect
AC
Waveforms.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
lect is Low, V
it is High, V
IH
V
Supply Voltage. The V
CC
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
V
Ground. The V
SS
all voltage measurements.
or
PHEL
117
Table 15.
and
Figure 15., Reset/
Waveforms, for
will temporarily unprotect the
ID
to V
must be slower than
IH
ID
. Ready/Busy is high-im-
OL
Table 15., Reset/
, the memory is in 8-bit mode, when
IL
, the memory is in 16-bit mode.
Supply Voltage
CC
.
CC3
Ground is the reference for
SS
harman/kardon
CC
Ground
SS

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