Fujitsu EVB JADE-­D Manual page 20

Interface board
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Prepared
Manfred Ortmann
Approved
Pin
118
119
120
121
122
123
124
125
126
127
128
Tab. 2­2: Pin assignment of connector X201, I/O signals side
 
Document Number
Checked
Date
2009­10­05
Signal
VCC18
1.8 V, regulated on XXSvideo­D
SDRAM
TRACECLK
Trace clock
VCC18
1.8 V, regulated on XXSvideo­D
SDRAM
GND
Ground at center pin
GND
Ground at center pin
GND
Ground at center pin
GND
Ground at center pin
GND
Ground at center pin
GND
Ground at center pin
GND
Ground at center pin
GND
Ground at center pin
Preliminary
Revision
Storage
PA 4.2
Mycable01
Function
20(45)
for DDR2 
 
for DDR2 
 

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