Fujitsu EVB JADE-­D Manual page 17

Prepared
Manfred Ortmann
Approved
Pin
34
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Document Number
Checked Date
2009­10­05
Signal
ADCGND
AD_VRL0
AD_VRH1
AD_VR0
AD_VIN1
AD_VIN0
AD_VRH0
GND
OPT_PIN_0
DISP_P_R_10
OPT_PIN_1
DISP_N_R_10
VCC12
DISP_P_R_7
VCC12
DISP_N_R_7
DISP_P_R_0
DISP_P_R_8
DISP_N_R_0
DISP_N_R_8
DISP_P_R_1
DISP_P_R_9
DISP_N_R_1
DISP_N_R_9
DISP_P_R_2
Preliminary
Revision Storage
PA 4.2 Mycable01
Function
Ground for ADC signals
Reference voltage "L" input
Reference voltage "H" input 1
Reference output
A/D analog input, channel 1
A/D analog input, channel 0
Reference voltage "H" input 0
Ground
A/D analog input, channel 2 or
TESTMODE 2
RSDS Output 10p, in TTL Mode
Default=DOUTB0_4
A/D analog input, channel 3 or
VINITHI
RSDS Output 10n, in TTL Mode
Default=DOUTB0_5
1.2 V from CPU core voltage regulator
RSDS Output 7p, in TTL Mode
Default=DOUTG0_6
1.2 V from CPU core voltage regulator
RSDS Output 7n, in TTL Mode
Default=DOUTG0_7
RSDS Output 0p, in TTL Mode
Default=DOUTR0_0
RSDS Output 8p, in TTL Mode
Default=DOUTB0_0
RSDS Output 0n, in TTL Mode
Default=DOUTR0_1
RSDS Output 8n, in TTL Mode
Default=DOUTB0_1
RSDS Output 1p, in TTL Mode
Default=DOUTR0_2
RSDS Output 9p, in TTL Mode
Default=DOUTB0_2
RSDS Output 1n, in TTL Mode
Default=DOUTR0_3
RSDS Output 9n, in TTL Mode
Default=DOUTB0_3
RSDS Output 2p, in TTL Mode
Default=DOUTR0_4
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