Chipset - SOYO SY-P4VSA User Manual

Motherboard Description SY-P4VSA
– (e.g., precharge other banks while accessing the current bank)
– Four cache lines (16 quadwords) of CPU to DRAM write buffers
– Four cache lines of CPU to DRAM read prefetch buffers
– Read around write capability for non-stalled CPU read
– Speculative DRAM read before snoop result
– Burst read and write operation
– x-1-1-1-1-1-1-1 back-to-back accesses for SDR SDRAM
– Decoupled and burst DRAM refresh with staggered RAS timing (CAS
before RAS or self refresh)

1-9 CHIPSET

P4X266
The P4X266 (VT8753) is a high performance, cost-effective and energy
efficient chip set for the implementation of desktop personal computer
systems computer systems with 400 MHz (100 MHz QDR) CPU host bus
("Front Side Bus") based on 64-bit Intel Pentium-IV super-scalar
processors.
The P4X266 chip set consists of the VT8753 system controller (664 pin
BGA) and the VT8233 V-Link south bridge (376 pin BGA). The VT8753
Host system controller is an update of VIA's VT8633 Apollo Pro266T
system controller that adds CPU bus extensions to support Pentium IV and
AGP bus extensions to support 8x transfer mode. The VT8753 provides
superior performance between the CPU, DRAM, V-Link bus and AGP 8x
graphics controller bus with pipelined, burst, and concurrent operation. The
VT8233 V-Link Client controller is a highly integrated PCI / LPC controller.
Its internal bus structure is based on 66 MHz PCI bus that provides 2x
bandwidth compare to previous generation PCI / ISA bridge chips. The
VT8233 also provides a 266MB/sec bandwidth Host/Client V-Link interface
with V-Link-PCI and V-Link-LPC controllers. It supports five PCI slots of
arbitration and decoding for all integrated functions and LPC bus.
The VT8753 supports eight banks of SDR SDRAM up to 4 GB for
registered modules (eight banks up to 2 GB for unbuffered modules). The
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