SOYO SY-P4VSA User Manual page 70

Mpga socket 478 processor supported via p4x266 agp/pci 400 mhz front side bus supported atx form factor
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BIOS Setup Utility
DRAM Clock/Drive Control
DRAM Clock
DRAM Timing
SDRAM Cycle
Length
Bank Interleave
Precharge to
Active(Trp)
Active to
Precharge
Active to
CMD(Trcd)
DRAM Burst Len
DRAM Command
Rate
Setting
100
133
By SPD
Manual
3
2
Disabled
2 Bank
4 Bank
2T
3T
6T
5T
3T
2T
4
8
1T Command
2T Command
66
Description
This item allows you to
control the DRAM speed.
If enable the DRAM will auto
detect the DRAM timing.
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency
depends on the DRAM
timing. Do not reset this field
from the default value
specified by the system
designer.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
SY-P4VSA
Note
Default
Default
Default
Default
Default
Default
Default
Default

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