Advanced Chipset Features - Abit AT8 32X User Manual

3-14

3-4. Advanced Chipset Features

► DRAM Configuration
► LDT & PCI Bus Control
System BIOS Cacheable
↑↓→←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
DRAM Configuration:
Click <Enter> key to enter its submenu:
DRAM Timing Selectable
X - DRAM Clock
X - CAS Latency Time
X - Row Cycle Time
X - Row Refresh Cycle Time
X - Min RAS# Active Time
X - RAS# to CAS# Delay
X - RAS# Precharge Time
X - RAS# to RAS# Delay
X - Write Recovery Time
X - Write to Read Delay
X - Read to Write Delay
X - DRAM Command Rate
X - Bank Interleaving
X - Burst Length
32 bit Dram Memory Hole
MTRR Mapping Mode
DRAM ECC Feature Control
X - ECC Memory Interlock
X - ECC MCE Enable
X - Chip-Kill Mode Enable
X - ECC Redirection
X - DRAM Scrub Rate
X - L2 Cache Scrub Rate
X - DCache Scrub Rate
↑↓→←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
DRAM Timing Selectable:
This item selects the DRAM timing mode. When set to "By SPD", the BIOS will read the DRAM module
AT8 32X
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
F6: Fail-Safe Defaults
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Configuration
F6: Fail-Safe Defaults
Press Enter
Press Enter
Enabled
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Enabled
4 beats
Auto
Continuous
Non-ECC
At Least One
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Item Help
F7: Optimized Defaults
Item Help
F7: Optimized Defaults
Chapter 3