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2.4 Advanced Chipset Features
K8<->NB HT Speed
K8<->NB HT Width
► DRAM Configuration
SSE/SSE2 Instructions
↓↑→←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
K8<->NB HT Speed
This item selects the LDT Bus Frequency between CPU and NF520 Chipset.
K8<->NB HT Width
This item selects the LDT Bus Width between CPU and NF520 Chipset.
DRAM Configuration
Click <Enter> key to enter its submenu.
You may manually set the DRAM timing parameters through its sub-items, or leave them at
their default settings according to the SPD (Serial Presence Detect) data stored in the DRAM.
SSE/SSE2 Instructions
This item allows you to Enable or Disable the SSE/SSE2 (Streaming SIMD Extensions)
instruction set.
AN52/AN52-E
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Auto
Auto
Press Enter
Enabled
F6: Fail-Safe Defaults
Item Help
F7: Optimized Defaults
2-9
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