Cpu Configuration - Foxconn D42S 3.0 User Manual

access the memory device.
Select [Enabled] for SPD enable mode.
Select [Disabled] to set the parameters by yourself.
The following 4 settings are valid only when the Configure DRAM Timing by SPD is set to
[Disabled].
► DRAM CAS# Latency
This item controls the CAS latency. The CAS Latency is the number of clock cycles that elapse
from the time the request for data is sent to the actual memory location until the data is transmit-
ted from the module.
► DRAM RAS# to CAS# Delay
This item allows you to select a delay time (in clock cycles) between the CAS and RAS strobe
signals.
► DRAM RAS# Precharge
This item allows you to select the DRAM RAS precharge time (in clock cycles).
► DRAM RAS# Activate to Precharge
This item allows you to set the precharge delay time (in clock cycles).

CPU Configuration

CPU Configuration
Module Version : 3F.1B
Manufacturer : Intel
Intel(R) Atom(TM) CPU D425
Frequency
FSB Speed
Cache L1
Cache L2
Ratio Actual Value:9
Execute-Disable Bit Capabili
Hyper Threading Technology
↑↓←→:Move Enter:Select
► Execute-Disable Bit Capabili
This item is used to enable/disable the Execute Disable Bit feature.
Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer
overflow attacks when combined with a supporting operating system.
Execute Disable Bit allows the processor to classify areas in memory by where application
code can execute and where it cannot. When a malicious worm attempts to insert code in the
buffer, the processor disables code execution, preventing damage and worm propagation.
CMOS Setup Utility - Copyright (C) 1985-2010, American Megatrends, Inc.
CPU Configuration
:1.80GHz
:800MHz
:24KB
:512KB
+/-/:Value
F9:Optimized Defaults
When disable, force
the XD feature flay to
@1.80GHz always return 0.
[Enabled]
[Enabled]
F10:Save ESC:Exit
25
Help Item
F1:General Help