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Table 13. System Power Management M-States
M States
M0
M1
M-off
The development board also supports CLKRUN#.
3.8
Testability
The development board provides an Extended Debug Port (XDP) for testing at J1F1
and direct processor probing. The XDP interface is backwards compatible with the
older ITP interface as well. The user must use an XDP or ITP interface that is
compatible with the Intel® Core™ 2 Duo processor SL9400 and SU9400
Note: The XDP interface is backwards compatible with the ITP interface. However, an XDP to
ITP converter cable is necessary to use the older ITP tools. Also, in some cases a
resistor change rework is necessary to get the older ITP tools to function properly.
Please contact your Intel representative for additional details.
3.9
Power Measurement Support
Power measurement resistors are provided on the platform to measure the power of
most subsystems. All power measurement resistors have a tolerance of 1%. The value
of these power measurement resistors are 2mΩ by default. Power on a particular
subsystem is calculated using the following formula:
2
V
=
P
R
R = value of the sense resistor (typically 0.002Ω)
V = the voltage difference measured across the sense resistor.
It is recommended that the user use a high precision digital multi-meter tool such as
the Agilent 34401A digital multi-meter. Refer to
precision digital multi-meter (Agilent 34401A) versus a standard precision digital
multi-meter (Fluke 79).
42
System
Power Wells
States
S0
All wells powered
S3-S5
Main well down
S3-S5
Main well down
Development Board Features
DRAM
Powered
Clock chip powered and PLL, DLL in use
In self refresh; ME
Clock Chip powered with only the GMCH
DRAM controller on
clock running and PLL, DLL in use
using Channel A
Powered off (or self
None, ME powered off
refresh)
T able 14
for a comparison of a high
2
Development Kit User's Manual
ME Clocking
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