Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Specification page 20

In a rare global fatal MCA corner case this issue could affect all threads. In this case
PAL will not be able to monitor the arrival of all threads at SAL_CHECK. For PAL to
monitor arrival of all threads, at least one thread must arrive at the PALE_CHECK
vector. An XPN timeout is likely to occur if the corner case condition happens due to
hang resulting from all threads failing to enter PALE_CHECK.
Status: No Fix.
26. DC Common Mode Clock At Rx Input For Intel
Problem: The Intel
Receiver Parameter Values for Intel
@ 4.8 GTs. The processor does not follow the minimum value of 125 mV documented in
the Intel
parameter in the table below. Instead it uses a Min value of 175 mV.
Symbol
V
Rx-
clock-cm-
pin
Implication: Min measured value does not comply with the Intel
Version 1.0, Electrical specifications and Intel Scalable Memory Interconnect Electrical
specifications.
Workaround: None at this time.
Status: No Fix.
27. North Bound Link Errors Followed Immediately By Erasure+1 Errors
Can Cause Correctable Error To Be Uncorrectable
Problem: The following sequence will cause the 2nd correctable ECC error (4th bullet) to be
logged as uncorrectable.
• Northbound Link error on rank A
• Followed immediately by Erasure +1 error on rank B (not rank A)
• Followed fairly quickly by another Northbound link error on rank C (C could be
same as A)
• Followed immediately by Erasure +1 error on a different rank (not rank C)
Erasure is where a DRAM is mapped out by the memory controller as it has exceeded
the number of correctable errors.
Implication: This issue is only expected to be seen during error injection testing.
Workaround: None at this time.
Status: No Fix.
28. Corrupted ALERT Frame Not Detected By Zbox
Problem: Any corrupted ALERT frame will not be detected by the processor. Since the
®
Intel 7500 Scalable Memory Buffer issues a series of ALERT frames, in most cases
missing an ALERT frame is not an issue. There is no CRC protection on ALERT frames,
and the processor does not have a mechanism to detect corrupt Alert Frames.
Implication: A rare corner case condition could occur due to this issue. This corner case has not
been seen on a real system and is expected to be a very rare event. When the memory
controller issues a write to the Intel 7500 Scalable Memory Buffer, the memory
controller waits a round trip latency to confirm the southbound command arrived at the
Intel 7500 Scalable Memory Buffer intact. In the event of a southbound Intel
20
November 2012
® ®
Itanium Processor 9300 Series and 9500 Series Datasheet defines the
®
QuickPath Interconnect, Version 1.0, Electrical specifications for the
Parameter Min
DC common mode
ranges at the Rx
175
input for any clock
channel
®
®
QuickPath Interconnect and Intel
Nom Max Units
350 mV
® ®
Intel Itanium Processor 9300 Series and 9500 Series
®
SMI and Intel QPI
®
SMI Channels
Notes Symbol
V
Rx-
2
clock-cm-
pin
®
QuickPath Interconnect,
®
SMI CRC
Specifiication Update