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Low Power Features
2.2.1
Dynamic FSB Frequency Switching
Dynamic FSB frequency switching effectively reduces the internal bus clock frequency
in half to further decrease the minimum processor operating frequency from the
Enhanced Intel SpeedStep Technology performance states and achieve the Super Low
Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz
and does not entail a change in the external bus signal (BCLK) frequency. Instead, both
the processor and (G)MCH internally lower their BCLK reference frequency to 50% of
the externally visible frequency. Both the processor and (G)MCH maintain a virtual
BCLK signal ("VBCLK") that is aligned to the external BCLK but at half the frequency.
After a downward shift, it would appear externally as if the bus is running with a
100-MHz base clock in all aspects, except that the actual external BCLK remains at
200 MHz. The transition into SuperLFM, a "down-shift", is done following a handshake
between the processor and (G)MCH. A similar handshake is used to indicate an "up-
shift", a change back to normal operating mode.
2.2.2
Intel® Dynamic Acceleration Technology
The processor supports Intel Dynamic Acceleration Technology mode on select
platforms. The Intel Dynamic Acceleration Technology mode feature allows one core of
the processor to temporarily operate at a higher frequency point when the other core is
inactive and the operating system requests increased performance. This higher
frequency is called the opportunistic frequency and the maximum rated operating
frequency is the guaranteed frequency.
Note:
Intel Core 2 Extreme processors do not support Intel Dynamic Acceleration mode.
Intel Dynamic Acceleration Technology mode enabling requires:
• Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state.
• Enhanced Multi-Threaded Thermal Management (EMTTM).
• Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via
BIOS.
When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be
active under certain internal conditions. In such a scenario the processor may draw a
Instantaneous current (I
average I
to the Processor DC Specifications section for more details.
2.3
Extended Low Power States
Extended low power states (CxE) optimize for power by forcibly reducing the
performance state of the processor when it enters a package low power state. Instead
of directly transitioning into the package low power state, the extended package low
power state first reduces the performance state of the processor by performing an
Enhanced Intel SpeedStep Technology transition down to the lowest operating point.
Upon receiving a break event from the package low power state, control returns to the
software while an Enhanced Intel SpeedStep Technology transition up to the initial
operating point occurs. The advantage of this feature is that it significantly reduces
leakage while in low power states.
Note:
Long-term reliability cannot be assured unless all the Extended Low Power states are
enabled.
Datasheet
CC_CORE_INST)
current is lesser than or equal to I
CC
for a short duration of t
current specification. Please refer
CCDES
; however, the
INST
19
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