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Chapter 1: Introduction
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Chipset Overview
Built upon the functionality
and the capability of the E7525 Tumwater
chipset, the X6DAL-B2/X6DAL-TB2 motherboard provides the performance
and feature set required for dual processor-based servers, with configura-
tion options optimized for communications, presentation, storage, computa-
tion or database applications. The Intel E7525 Tumwater chipset consists
of the following components: the E7525 Tumwater Memory Controller Hub
(MCH), and the 6300ESB (Hance Rapids) I/O Controller Hub (Hance Rapids
ICH).
The E7525 Tumwater MCH supports single or dual Xeon EM64T (Nocona)
processors with Front Side Bus speeds of 800 MHz. Its memory controller
provides direct connection to two channels of registered DDRII 400 with a
marched system bus address and data bandwidths of up to 2.67 GB/s per
channel. The E7525 Tumwater also supports the new PCI Express high
speed serial I/O interface for superior I/O bandwidth.
These interfaces
support connection of the MCH to a variety of other bridges that are com-
pliant with the PCI Express Interface Specification.
The MCH interfaces
with the 6300ESB (Hance Rapids) ICH I/O Controller Hub via HI 1.5 Hub
Interface. The 6300ESB provides two PCI bus interfaces that can be con-
figured for standard PCI 2.2 protocol, as well as the enhanced high-fre-
quency PCI-X protocol.
6300ESB (Hance Rapids) ICH System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the Hance Rapids ICH I/O Controller Hub
integrates many
I/O
functions.
The Hance Rapids ICH I/O Controller Hub integrates: 2-channel Ultra ATA/
100 Bus Master IDE Controller, two Serial ATA (SATA) Host Controllers,
SMBus 2.0 Controller, LPC/Flash BIOS Interface, PCI-X (66MHz)/PCI-Express
(x16 at 4GB/s) Interface, PCI 2.2 Interface and System Management Con-
troller.
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