Intel i960 Jx Developer's Manual page 58

Microprocessor
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PROGRAMMING ENVIRONMENT
Table 3-4. Supervisor Space Family Registers
Register Name
(PMCON0_1) Physical Memory Control Register 0
Reserved
(PMCON2_3) Physical Memory Control Register 1
Reserved
(PMCON4_5) Physical Memory Control Register 2
Reserved
(PMCON6_7) Physical Memory Control Register 3
Reserved
(PMCON8_9) Physical Memory Control Register 4
Reserved
(PMCON10_11) Physical Memory Control Register 5
Reserved
(PMCON12_13) Physical Memory Control Register 6
Reserved
(PMCON14_15) Physical Memory Control Register 7
Reserved
(BCON) Bus Configuration Control Register
(PRCB) Processor Control Block Pointer
(ISP) Interrupt Stack Pointer
(SSP) Supervisor Stack Pointer
Reserved
(DEVICEID) i960 Jx processor Device ID
Reserved
3-10
(Sheet 2 of 2)
Memory-Mapped
Access Type
Address
FF00 8600H
FF00 8604H
FF00 8608H
FF00 860CH
FF00 8610H
FF00 8614H
FF00 8618H
FF00 861CH
FF00 8620H
FF00 8624H
FF00 8628H
FF00 862CH
FF00 8630H
FF00 8634H
FF00 8638H
FF00 863CH to
FF00 86F8H
FF00 86FCH
FF00 8700H
FF00 8704H
FF00 8708H
FF00 870CH
FF00 8710H
FF00 8714H to
FFFF FFFFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
RO

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