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INTERRUPTS
Since interrupts are handled based on priority, requested interrupts are often saved for later service
rather than being handled immediately. The mechanism for saving the interrupt is referred to as
interrupt posting. Interrupt posting is described in
The i960 core architecture defines two data structures to support interrupt processing: the interrupt
table (see
Figure
11-1) and interrupt stack. The interrupt table contains 248 vectors for interrupt
handling procedures (eight of which are reserved) and an area for posting software-requested
interrupts. The interrupt stack prevents interrupt handling procedures from using the stack in use
by the application program. It also allows the interrupt stack to be located in a different area of
memory than the user and supervisor stack (e.g., fast SRAM).
®
i960
Jx
Interrupt
Request
Processor
Figure 11-1. Interrupt Handling Data Structures
®
11.1.1
The i960
Jx Processor Interrupt Controller
The i960 Jx processor Interrupt Controller Unit (ICU) provides a flexible, low-latency means for
requesting and posting interrupts and minimizing the core's interrupt handling burden. Acting
independently from the core, the interrupt controller posts interrupts requested by hardware and
software sources and compares the priorities of posted interrupts with the current process priority.
The interrupt controller provides the following features for managing hardware-requested interrupts:
•
Low latency, high throughput handling
•
Support of up to 240 external sources
•
Eight external interrupt pins, one non-maskable interrupt pin, two internal timers sources for
detection of hardware-requested interrupts
•
Edge or level detection on external interrupt pins
•
Debounce option on external interrupt pins
The user program interfaces to the interrupt controller with six memory-mapped control registers.
The interrupt control register (ICON) and interrupt map control registers (IMAP0-IMAP2)
provide
configuration
information.
hardware-requested interrupts. The interrupt mask (IMSK) register selectively masks
hardware-requested interrupts.
11-2
section 11.6.5, "Posting Interrupts" (pg.
Memory
Interrupt
Table
Interrupt Pointer
The
interrupt
pending
11-9).
Interrupt
Handling
Procedure
(IPND)
register
posts
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