Interface Circuit - Epson LQ-300 Service Manual

2.3.10 Interface Circuit

Figure 2-21 shows the parallel interface arcuit block diagram. Data from the host computer is
latched within the gate array by STROBE signal.
automatically to stop the host computer from sending further data. The gate array reads the data
latched periodically with generating an interrupt.
The parallel I/F conforms to bidirectional parallel I/F IEEE-P1284 level 1 nibble mode.
Figure 2-21. Parallel Interface Block Diagram
the serial
driver/receiver IC4. Data is transmitted to an input buffer in IC1l from the CPU. Printing starts
when a CR code is received or when the input buffer is filled.
Serial IIF
TXD 4
DTR 4
CTS
RST
Figure 2-22. Serial Interface
Parallel l/F
127-134
4
4
interface circuit block diagram. The serial interface conforms to
Driver/Receiver
. D1OUT
D21N
R1OUT
The gate array outputs XBUSY signal
Array (IC2)
Gate
DINO-7
39
:
13
- - - -
12 '
14
------ XERR
15
------ XSLCT
4
- - - -
"
CPU (lCl)
53
P33
52
P32
50
P30
54
P34
Block Diagram
Operating Principles
2-17