Epson LQ-510 Technical Manual page 200

APPENDIX
CPU Timing
Refer to Figures A-3 through A-5 for CPU timing diagrams. Three oscillations define one state. The OP code
fetch requires four states. During T1 to T3, program memory is read, and instructions are interpreted during
T4. Address bus lines 15-8 are output from T1 to T4. Address bus lines 7-0 (PD7-0) are used in the multiplex
mode. The address is latched during T1 at the ALE signal.
Since the memory addressed is enabled after disengaging the driver (AD7-0), RD is output from T1-T3, fet-
ched at T3, and processed internally at T4. The ALE and RD signals are executed from T1-T3, and the OP
code fetch for these two signals is performed at T4. The WR signal is output from the middle of T1 to the
beginning of T3. The address and ALE timing is the same as that for memory read; however, following
address output, AD7-0 (PD7-0) are not disabled, and write data is output at AD7-0 at the beginning of T1
and at the end of T3.
NOTE: When PD7-0 are set to the multiplexed address/data bus (AD7-0) and PF7-0 to the address bus
(AB7-0), the RD and WR signals in the machine cycle are HIGH when memory is not being accessed.
CLOCK
ALE
A B 1 5 - 8
(PF7 - 0)
AD7-0
-
(PD7
A-6
I
T1
Y
0)
Figure A-3. OP Code Fetch Timing
CLOCK
A B 1 5 - 8
X
(PF7 - 0)
A D 7 - 0
(PD7 -0)
Figure A-4. Memory Read Timing
CLOCK
ALE J
A B 1 5 - 8
X
(PF7 - 0)
A D 7 - 0
ADDRESS
(PD7 - 0)
Figure A-5. Memory Write Timing
T3
T2
ADDRESS
OP
CODE
ADDRESS
ADDRESS
WRITE DATA
T4
X
X
X
X
REV.-A
LQ-510