Typical Timing Diagram - Nintendo DMG-01 - Game Boy Console Manual

TM
Game Boy CPU Manual

5.2. Typical timing diagram

(Based on an email from Philippe Pouliquen)
The graphic shows a write followed by two reads
(measured on a regular GameBoy):
_________
CLK:____/
_________________
/RD:_______/
______________
/WR:
__________
/CS: \_____________/
Adr:_______ ___________________ ___________________ __________________ _
Bus:_______X___________________X___________________X__________________X_
Dta:
Bus:--------------<_________>---------<_________>---------<_________>---
^ ^ ^
Time: a b c
Timing:
a: 0ns
this is the point at which CLK goes high, from which
the other times are measured.
b: 140ns
point at which /RD will rise before a write. This is
also the point at which the address on the address
bus changes.
c: 240ns
point at which /CS goes low (this is pin 5 of the
connector)
d: 480ns
point at which CLK goes low. This is also the point
at which /WR goes low for a write and the GameBoy
starts driving the data bus.
e: 840ns
by DP
_________
\_________/
\__________________________________________
_____________________________________________
\_______/
_____
_________
^ ^ ^^
d e fg
5.2. Typical timing diagram
_________
\_________/
_____
\_____________/
_________
___
\_________/
___
\_____________/
_________
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