Ide Support; Real-Time Clock, Cmos Sram, And Battery; I/O Controller - Intel D865PCK Specification

Intel Desktop Board D865PCK Technical Product Specification

1.5.3 IDE Support

The board provides two Parallel ATA IDE connectors, which support a total of four devices (two
per connector). The ICH5's Parallel ATA IDE controller has two independent bus-mastering
Parallel ATA IDE interfaces that can be independently enabled. The Parallel ATA IDE interfaces
support the following modes:
•
Programmed I/O (PIO): processor controls data transfer.
•
8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
•
Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
•
ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
•
ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH5's ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.
NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The Parallel ATA IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA
devices.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
For information about
The location of the Parallel ATA IDE connectors

1.5.4 Real-Time Clock, CMOS SRAM, and Battery

A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
RAM at power-on.

1.6 I/O Controller

The I/O controller provides the following features:
•
One serial port
•
One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
•
Serial IRQ interface compatible with serialized IRQ support for PCI systems
20
Refer to
Figure 11, page 45