Table of Contents
Advertisement
Errata
BH1
An xTPR Update Transaction Cycle, if Enabled, May be Issued to the
FSB after the Processor has Issued a Stop-Grant Special Cycle
Problem:
According to the FSB (Front Side Bus) protocol specification, no FSB cycles should be
issued by the processor once a Stop-Grant special cycle has been issued to the bus. If
xTPR update transactions are enabled by clearing the IA32_MISC_ENABLES[bit-23] at
the time of Stop-Clock assertion, an xTPR update transaction cycle may be issued to
the FSB after the processor has issued a Stop Grant Acknowledge transaction.
Implication: When this erratum occurs in systems using C-states C2 (Stop-Grant State) and higher
the result could be a system hang.
Workaround: BIOS must leave the xTPR update transactions disabled (default).
Status:
For the steppings affected, see the Summary Tables of Changes.
BH2
Processor May Report a #TS Instead of a #GP Fault
Problem:
During system reset, there is insufficient time for handshake between ICH and GMCH
LVDS logic. As a result, timing from panel backlight enable going low to LVDS data
going low (TX) and timing from LVDS data going low to panel VCC enable going low
(T3) do not match the programmed values. Panel backlight enable (LBKLT_EN), panel
Vcc enable (LVDD_EN) and LVDS data lines go low at the same time.
Implication: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Workaround: None.
Status:
For the steppings affected, see the Summary Tables of Changes.
14
Errata
Specification Update
Advertisement
Table of Contents
